8(~Hradxa,rock-s0rockchip,rk3308 +7Radxa ROCK S0aliases=/pinctrl/gpio@ff220000C/pinctrl/gpio@ff230000I/pinctrl/gpio@ff240000O/pinctrl/gpio@ff250000U/pinctrl/gpio@ff260000[/i2c@ff040000`/i2c@ff050000e/i2c@ff060000j/i2c@ff070000o/serial@ff0a0000w/serial@ff0b0000/serial@ff0c0000/serial@ff0d0000/serial@ff0e0000/spi@ff120000/spi@ff130000/spi@ff140000/ethernet@ff4e0000/mmc@ff490000/mmc@ff480000/mmc@ff4a0000cpus+cpu@0cpuarm,cortex-a35psciZ !1BMcpu@1cpuarm,cortex-a35psci !1Mcpu@2cpuarm,cortex-a35psci !1M cpu@3cpuarm,cortex-a35psci !1M idle-statesUpscicpu-sleeparm,idle-statebsxMl2-cachecacheMopp-table-0operating-points-v2Mopp-408000000Q ~~r`@opp-600000000#F ~~r`@opp-8160000000, r`@opp-1008000000< **r`@arm-pmuarm,cortex-a35-pmu0STUV external-mac-clock fixed-clock1 Amac_clkinTpsci arm,psci-1.0smctimerarm,armv8-timer0   xin24m fixed-clockT1n6Axin24mM^grf@ff000000&rockchip,rk3308-grfsysconsimple-mfdM9io-domains"rockchip,rk3308-io-voltage-domainaokayh v     reboot-modesyscon-reboot-modeRBRBRBRBRB syscon@ff008000.rockchip,rk3308-usb2phy-grfsysconsimple-mfd@+usb2phy@100rockchip,rk3308-usb2phy H.phyclk Ausb480m_phyTaokayM otg-port$CDE:otg-bvalidotg-idlinestateJaokayM?host-port J :linestateJaokayM@syscon@ff00b000-rockchip,rk3308-detect-grfsysconsimple-mfd+syscon@ff00c000+rockchip,rk3308-core-grfsysconsimple-mfd+i2c@ff040000(rockchip,rk3308-i2crockchip,rk3399-i2c .i2cpclk  Udefaultc+ adisabledi2c@ff050000(rockchip,rk3308-i2crockchip,rk3399-i2c .i2cpclk  Udefaultc+ adisabledi2c@ff060000(rockchip,rk3308-i2crockchip,rk3399-i2c .i2cpclk  Udefaultc+ adisabledi2c@ff070000(rockchip,rk3308-i2crockchip,rk3399-i2c .i2cpclk Udefaultc+ adisabledwatchdog@ff080000 rockchip,rk3308-wdtsnps,dw-wdt  aokayserial@ff0a0000&rockchip,rk3308-uartsnps,dw-apb-uart  .baudclkapb_pclkmwUdefaultcaokayserial@ff0b0000&rockchip,rk3308-uartsnps,dw-apb-uart  .baudclkapb_pclkmwUdefault c adisabledserial@ff0c0000&rockchip,rk3308-uartsnps,dw-apb-uart  .baudclkapb_pclkmwUdefaultc adisabledserial@ff0d0000&rockchip,rk3308-uartsnps,dw-apb-uart  .baudclkapb_pclkmwUdefaultc adisabledserial@ff0e0000&rockchip,rk3308-uartsnps,dw-apb-uart .baudclkapb_pclkmwUdefault caokaybluetoothbrcm,bcm43430a1-bt.lpo   :host-wakeup    Udefault c  spi@ff120000(rockchip,rk3308-spirockchip,rk3066-spi +.spiclkapb_pclktxrxUdefaultc !"# adisabledspi@ff130000(rockchip,rk3308-spirockchip,rk3066-spi +.spiclkapb_pclktxrxUdefaultc$%&' adisabledspi@ff140000(rockchip,rk3308-spirockchip,rk3066-spi +.spiclkapb_pclk((txrxUdefaultc)*+, adisabledpwm@ff160000(rockchip,rk3308-pwmrockchip,rk3328-pwmy .pwmpclkUdefaultc- adisabledpwm@ff160010(rockchip,rk3308-pwmrockchip,rk3328-pwmy .pwmpclkUdefaultc. adisabledpwm@ff160020(rockchip,rk3308-pwmrockchip,rk3328-pwm y .pwmpclkUdefaultc/ adisabledpwm@ff160030(rockchip,rk3308-pwmrockchip,rk3328-pwm0y .pwmpclkUdefaultc0 adisabledpwm@ff170000(rockchip,rk3308-pwmrockchip,rk3328-pwmx .pwmpclkUdefaultc1 adisabledpwm@ff170010(rockchip,rk3308-pwmrockchip,rk3328-pwmx .pwmpclkUdefaultc2 adisabledpwm@ff170020(rockchip,rk3308-pwmrockchip,rk3328-pwm x .pwmpclkUdefaultc3 adisabledpwm@ff170030(rockchip,rk3308-pwmrockchip,rk3328-pwm0x .pwmpclkUdefaultc4 adisabledpwm@ff180000(rockchip,rk3308-pwmrockchip,rk3328-pwm .pwmpclkUdefaultc5aokayMmpwm@ff180010(rockchip,rk3308-pwmrockchip,rk3328-pwm .pwmpclkUdefaultc6 adisabledpwm@ff180020(rockchip,rk3308-pwmrockchip,rk3328-pwm  .pwmpclkUdefaultc7 adisabledpwm@ff180030(rockchip,rk3308-pwmrockchip,rk3328-pwm0 .pwmpclkUdefaultc8 adisabledrktimer@ff1a0000rockchip,rk3288-timer   .pclktimersaradc@ff1e0000.rockchip,rk3308-saradcrockchip,rk3399-saradc %%.saradcapb_pclkF saradc-apbaokay efuse@ff210000rockchip,rk3308-otp!@+'.otpapb_pclkphyTphyid@7cpu-leakage@17logic-leakage@18dma-controller@ff2c0000arm,pl330arm,primecell,@ .apb_pclk2Mdma-controller@ff2d0000arm,pl330arm,primecell-@ .apb_pclk2M(i2s@ff320000rockchip,rk3308-i2s-tdm2 2.mclk_txmclk_rxhclkTV((rxtx tx-mrx-m=9 adisabledi2s@ff330000rockchip,rk3308-i2s-tdm3 3.mclk_txmclk_rxhclkXZ(rx tx-mrx-m=9 adisabledi2s@ff350000(rockchip,rk3308-i2srockchip,rk3066-i2s5 4\.i2s_clki2s_hclk(( txrxreset-mreset-hUdefaultc:;<= adisabledi2s@ff360000(rockchip,rk3308-i2srockchip,rk3066-i2s6 5^.i2s_clki2s_hclk( rxreset-mreset-h adisabledspdif-tx@ff3a0000,rockchip,rk3308-spdifrockchip,rk3066-spdif: 7b .mclkhclk( txUdefaultc> adisabledusb@ff4000002rockchip,rk3308-usbrockchip,rk3066-usbsnps,dwc2@ B.otg JperipheralRds@ ? usb2-phyaokayusb@ff440000 generic-ehciD G @usbaokayusb@ff450000 generic-ohciE H @usbaokaymmc@ff4800000rockchip,rk3308-dw-mshcrockchip,rk3288-dw-mshcH@ L 012.biuciuciu-driveciu-sampleрUdefaultcABCDaokayEmmc@ff4900000rockchip,rk3308-dw-mshcrockchip,rk3288-dw-mshcI@ M :;<.biuciuciu-driveciu-sampleрaokayUdefaultcFGHI mmc@ff4a00000rockchip,rk3308-dw-mshcrockchip,rk3288-dw-mshcJ@ N 567.biuciuciu-driveciu-sampleUdefault cJKLaokay+ -M8 ? wifi@1'brcm,bcm43430a1-fmacbrcm,bcm4329-fmac N :host-wakeUdefaultcOnand-controller@ff4b0000(rockchip,rk3308-nfcrockchip,rv1108-nfcK@ Q-.ahbnfc-LрcPQRSTUVUdefault adisabledethernet@ff4e0000rockchip,rk3308-gmacN @:macirq@@BBA@C[.stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macclk_mac_speedarmiiUdefaultcWX} stmmaceth=9aokayjoutputwY mdiosnps,dwmac-mdio+ethernet-phy@1ethernet-phy-ieee802.3-c22UdefaultcZN P NMYspi@ff4c0000 rockchip,sfcL@ R=.clk_sfchclk_sfc c[\]Udefault adisabledclock-controller@ff500000rockchip,rk3308-cruP^.xin24m=9TLMcodec@ff560000rockchip,rk3308-codecV=9.mclk_txmclk_rxhclkUWcodec adisabledinterrupt-controller@ff580000 arm,gic-400@XX X@ X`   Msram@fff80000 mmio-sram+ddr-sram@0vad-sram@8000pinctrlrockchip,rk3308-pinctrl=9+Udefaultc_gpio@ff220000rockchip,gpio-bank" (MNgpio@ff230000rockchip,gpio-bank# )gpio@ff240000rockchip,gpio-bank$ *gpio@ff250000rockchip,gpio-bank% +gpio@ff260000rockchip,gpio-bank& ,Mpcfg-pull-up"Mipcfg-pull-down/Mfpcfg-pull-none>Mbpcfg-pull-none-2ma>Kpcfg-pull-up-2ma"Kpcfg-pull-up-4ma"KMhpcfg-pull-none-4ma>KMgpcfg-pull-down-4ma/Kpcfg-pull-none-8ma>KM`pcfg-pull-up-8ma"KMapcfg-pull-none-12ma>K Mdpcfg-pull-up-12ma"K Mcpcfg-pull-none-smt>ZMepcfg-output-highopcfg-output-low{pcfg-input-high"pcfg-inputemmcemmc-clk `MGemmc-cmdaMHemmc-pwren bMIemmc-rstn bemmc-bus1aemmc-bus4@aaaaemmc-bus8aaaaaaaaMFflashflash-csn0 bMSflash-rdy bMUflash-ale bMPflash-cle bMRflash-wrnbMVflash-rdn bMTflash-bus8ccccccccMQsfcsfc-bus4@bbbbM]sfc-bus2 bbsfc-cs0bM\sfc-clkbM[gmacrmii-pinsdddbbbbb bMWmac-refclk-12ma dMXmac-refclk bmac-rstbMZgmac-m1rmiim1-pinsdddbbbbb bmacm1-refclk-12ma dmacm1-refclk bi2c0i2c0-xfer eeMi2c1i2c1-xfer  e eMi2c2i2c2-xfer eeMi2c3-m0i2c3m0-xfer eeMi2c3-m1i2c3m1-xfer  e ei2c3-m2i2c3m2-xfer eei2s_2ch_0i2s-2ch-0-mclk bi2s-2ch-0-sclk bM:i2s-2ch-0-lrckbM;i2s-2ch-0-sdobM=i2s-2ch-0-sdibM<i2s_8ch_0i2s-8ch-0-mclkbi2s-8ch-0-sclktxbi2s-8ch-0-sclkrxbi2s-8ch-0-lrcktxbi2s-8ch-0-lrckrxbi2s-8ch-0-sdo0 bi2s-8ch-0-sdo1 bi2s-8ch-0-sdo2 bi2s-8ch-0-sdo3 bi2s-8ch-0-sdi0 bi2s-8ch-0-sdi1bi2s-8ch-0-sdi2bi2s-8ch-0-sdi3bi2s_8ch_1_m0i2s-8ch-1-m0-mclkbi2s-8ch-1-m0-sclktxbi2s-8ch-1-m0-sclkrxbi2s-8ch-1-m0-lrcktxbi2s-8ch-1-m0-lrckrxbi2s-8ch-1-m0-sdo0bi2s-8ch-1-m0-sdo1-sdi3bi2s-8ch-1-m0-sdo2-sdi2 bi2s-8ch-1-m0-sdo3_sdi1 bi2s-8ch-1-m0-sdi0 bi2s_8ch_1_m1i2s-8ch-1-m1-mclk bi2s-8ch-1-m1-sclktx bi2s-8ch-1-m1-sclkrxbi2s-8ch-1-m1-lrcktxbi2s-8ch-1-m1-lrckrxbi2s-8ch-1-m1-sdo0bi2s-8ch-1-m1-sdo1-sdi3bi2s-8ch-1-m1-sdo2-sdi2bi2s-8ch-1-m1-sdo3_sdi1bi2s-8ch-1-m1-sdi0bpdm_m0pdm-m0-clkbpdm-m0-sdi0 bpdm-m0-sdi1 bpdm-m0-sdi2 bpdm-m0-sdi3bpdm_m1pdm-m1-clkbpdm-m1-sdi0bpdm-m1-sdi1bpdm-m1-sdi2bpdm-m1-sdi3bpdm_m2pdm-m2-clkmbpdm-m2-clkbpdm-m2-sdi0 bpdm-m2-sdi1bpdm-m2-sdi2bpdm-m2-sdi3bpwm0pwm0-pin bpwm0-pin-pull-down fM5pwm1pwm1-pinbM6pwm1-pin-pull-downfpwm2pwm2-pinbM7pwm2-pin-pull-downfpwm3pwm3-pinbM8pwm3-pin-pull-downfpwm4pwm4-pinbM1pwm4-pin-pull-downfpwm5pwm5-pinbM2pwm5-pin-pull-downfpwm6pwm6-pinbM3pwm6-pin-pull-downfpwm7pwm7-pinbM4pwm7-pin-pull-downfpwm8pwm8-pin bM-pwm8-pin-pull-down fpwm9pwm9-pin bM.pwm9-pin-pull-down fpwm10pwm10-pin bM/pwm10-pin-pull-down fpwm11pwm11-pinbM0pwm11-pin-pull-downfrtcrtc-32kbM_sdmmcsdmmc-clkgMAsdmmc-cmdhMBsdmmc-dethMCsdmmc-pwrengsdmmc-bus1hsdmmc-bus4@hhhhMDsdmmc-2030bMlsdiosdio-clk`MLsdio-cmdaMKsdio-pwren`sdio-wrpt`sdio-intn`sdio-bus1asdio-bus4@aaaaMJspdif_inspdif-inbspdif_outspdif-outbM>spi0spi0-clkhM spi0-csn0hM!spi0-misohM"spi0-mosihM#spi1spi1-clk hM$spi1-csn0 hM%spi1-miso hM&spi1-mosi hM'spi1-m1spi1m1-misohspi1m1-mosihspi1m1-clkhspi1m1-csn0 hspi2spi2-clkhM)spi2-csn0hM*spi2-misohM+spi2-mosihM,tsadctsadc-otp-pin btsadc-otp-out buart0uart0-xfer iiMuart0-ctsbuart0-rtsbuart0-rts-pinbuart1uart1-xfer iiMuart1-ctsbMuart1-rtsbMuart2-m0uart2m0-xfer iiMuart2-m1uart2m1-xfer iiuart3uart3-xfer  i iMuart3-m1uart3m1-xfer iiuart4uart4-xfer  iiMuart4-ctsbMuart4-rtsbMuart4-rts-pinbbluetoothbt-reg-on bMbt-wake-host fMhost-wake-bt bMledspwr-ledbMjwifiwifi-reg-onbMnwifi-wake-hostfMOchosenserial0:1500000n8leds gpio-ledsUdefaultcjled-greenon heartbeat N heartbeatregulator-1v04-vdd-logregulator-fixedvdd_logހ-ހEkregulator-1v5-vcc-ddrregulator-fixedvcc_ddr`-`Ekregulator-1v8-vccregulator-fixedvcc_1v8w@-w@E M regulator-3v3-vcc-ioregulator-fixedvcc_io2Z-2ZEkM regulator-3v3-vcc-sdregulator-fixed Udefaultclvcc_sd2Z-2ZE MEregulator-5v0-vcc-sysregulator-fixed vcc5v0_sysLK@-LK@Mkregulator-vdd-corepwm-regulatorPmUk vdd_core x-r``Msdio-pwrseqmmc-pwrseq-simpleUdefaultcn NMM compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3serial0serial1serial2serial3serial4spi0spi1spi2ethernet0mmc0mmc1mmc2device_typeregenable-methodclocks#cooling-cellsdynamic-power-coefficientoperating-points-v2cpu-idle-statesnext-level-cachecpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendinterruptsinterrupt-affinityclock-frequencyclock-output-names#clock-cellsstatusvccio0-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyoffsetmode-bootloadermode-loadermode-normalmode-recoverymode-fastbootassigned-clocksassigned-clock-parentsclock-namesinterrupt-names#phy-cellspinctrl-namespinctrl-0reg-shiftreg-io-widthuart-has-rtsctsdevice-wakeup-gpiosshutdown-gpiosvbat-supplyvddio-supplydmasdma-names#pwm-cells#io-channel-cellsresetsreset-namesvref-supplyarm,pl330-periph-burst#dma-cellsrockchip,grfdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephysphy-namesbus-widthfifo-depthmax-frequencycap-mmc-highspeedcap-sd-highspeeddisable-wpvmmc-supplyno-sdno-sdionon-removablecap-sdio-irqkeep-power-in-suspendmmc-pwrseqno-mmcvqmmc-supplyassigned-clock-ratesphy-modeclock_in_outphy-handlephy-supplyreset-assert-usreset-deassert-usreset-gpios#reset-cells#sound-dai-cells#interrupt-cellsinterrupt-controllerrangesgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enableoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathcolordefault-statefunctionlinux,default-triggerregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltvin-supplypwmspwm-supplyregulator-settling-time-up-us