C89<( 9%mediatek,mt8195-demomediatek,mt8195 +7MediaTek MT8195 demo boardaliases=/soc/dp-intf@1c015000F/soc/dp-intf@1c113000O/soc/mailbox@10320000T/soc/mailbox@10330000Y/soc/hdr-engine@1c114000`/soc/mutex@1c016000g/soc/mutex@1c101000n/soc/vpp-merge@1c10c000u/soc/vpp-merge@1c10d000|/soc/vpp-merge@1c10e000/soc/vpp-merge@1c10f000/soc/vpp-merge@1c110000/soc/dma-controller@1c104000/soc/dma-controller@1c105000/soc/dma-controller@1c106000/soc/dma-controller@1c107000/soc/dma-controller@1c108000/soc/dma-controller@1c109000/soc/dma-controller@1c10a000/soc/dma-controller@1c10b000/soc/serial@11001100cpus+cpu@0cpuarm,cortex-a55psci#ec3@34FVc@u@ cpu@100cpuarm,cortex-a55psci#ec3@34FVc@u@ cpu@200cpuarm,cortex-a55psci#ec3@34FVc@u@ cpu@300cpuarm,cortex-a55psci#ec3@34FVc@u@ cpu@400cpuarm,cortex-a78psci#f3FVc@u@ cpu@500cpuarm,cortex-a78psci#f3FVc@u@cpu@600cpuarm,cortex-a78psci#f3FVc@u@cpu@700cpuarm,cortex-a78psci#f3FVc@u@cpu-mapcluster0core0 core1 core2 core3 core4 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mediatek,mt8195-topckgensysconsyscon@10001000#mediatek,mt8195-infracfg_aosysconosyscon@10003000mediatek,mt8195-pericfgsyscon0;pinctrl@10005000mediatek,mt8195-pinctrlPB|iocfg0iocfg_bmiocfg_bliocfg_briocfg_lmiocfg_rbiocfg_tleintQ[)eth-default-pins7pins-txdMNOPpins-ccUXWVpins-rxdQRSTpins-mdioYZpins-power[\eth-sleep-pins8pins-txdMNOPpins-ccUXWVpins-rxdQRSTpins-mdioYZgpio-keys-pinspinsji2c6-pinsOpinsmmc0-default-pins>pins-clkzfpins-cmd-dat$~}|{wvutyepins-rstxemmc0-uhs-pins?pins-clkzfpins-cmd-dat$~}|{wvutyepins-dsfpins-rstxemmc1-default-pinsBpins-clkofpins-cmd-datnpqrsepins-insertmmc1-uhs-pinsCpins-clkofpins-cmd-datnpqrseuart0-pins.pinsbcuart1-pins/pinsfgsyscon@10006000)mediatek,mt8195-scpsyssysconsimple-mfd`power-controller!mediatek,mt8195-power-controller+*power-domain@8+power-domain@9 (mfgalt4+power-domain@10 power-domain@11 power-domain@12 power-domain@13 power-domain@14power-domain@15 @AK   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'8defaultsleep78mdiosnps,dwmac-mdio+ethernet-phy@16stmmac-axi-config3rx-queues-config4queue0 queue1 queue2 queue3 tx-queues-config4J5queue0\ hqueue1\ hqueue2\ hqueue3\ husb@11201000#mediatek,mt8195-mtu3mediatek,mtu3  - > |macippc ?+[/B(sys_ckref_ckmcu_ckv9:{ ;gkokay<usb@0'mediatek,mt8195-xhcimediatek,mtk-xhci|mac[^,-n$/B$(sys_ckref_ckmcu_ckdma_ckxhci_ckkokay=mmc@11230000(mediatek,mt8195-mmcmediatek,mt8183-mmc #[(sourcehclksource_cgkokaydefaultstate_uhs>? !L0@<AImmc@11240000(mediatek,mt8195-mmcmediatek,mt8183-mmc $[$(sourcehclksource_cg^nkokaydefaultstate_uhsBC W `q~0D<Emmc@11250000(mediatek,mt8195-mmcmediatek,mt8183-mmc %[ I(sourcehclksource_cg^ n kdisabledthermal-sensor@11278000mediatek,mt8195-lvts-mcu'[01$lvts-calib-data-1lvts-calib-data-2usb@11290000'mediatek,mt8195-xhcimediatek,mtk-xhci ))> |macippc[vFG^./n$''$(sys_ckref_ckmcu_ckdma_ckxhci_ck ;h{kokay<usb@112a1000#mediatek,mt8195-mtu3mediatek,mtu3 *-*> |macippc*?+[^0n''(sys_ckref_ckmcu_ckvH{ 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RUlarb@1c018000mediatek,mt8195-smi-larb  t((  (apbsmigals`*larb@1c019000mediatek,mt8195-smi-larb  d(  (apbsmigals`*fsyscon@1c100000mediatek,mt8195-vdosys1syscon y :o#smi@1c01b000mediatek,mt8195-smi-common-vdo %&)$(apbsmigals0gals1`*tiommu@1c01f000mediatek,mt8195-iommu-vdo8 [G'(bclk`*umutex@1c101000mediatek,mt8195-disp-mutex[`*# : Rlarb@1c102000mediatek,mt8195-smi-larb   t### (apbsmigals`*larb@1c103000mediatek,mt8195-smi-larb0  d##  (apbsmigals`*gdma-controller@1c104000mediatek,mt8195-vdo1-rdma@[#`* su@ :@ zdma-controller@1c105000mediatek,mt8195-vdo1-rdmaP[#`* sc` :P zdma-controller@1c106000mediatek,mt8195-vdo1-rdma`[#`* suA :` zdma-controller@1c107000mediatek,mt8195-vdo1-rdmap[#`* sca :p zdma-controller@1c108000mediatek,mt8195-vdo1-rdma[#`* suB : zdma-controller@1c109000mediatek,mt8195-vdo1-rdma[#`* scb : zdma-controller@1c10a000mediatek,mt8195-vdo1-rdma[#`* suC : zdma-controller@1c10b000mediatek,mt8195-vdo1-rdma[#`* scc : zvpp-merge@1c10c000mediatek,mt8195-disp-merge[# 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" . criticalcooling-mapsmap0 90 > cpu2-thermal   tripstrip-alert "L .passivetrip-crit " . criticalcooling-mapsmap0 90 > cpu3-thermal   tripstrip-alert "L .passivetrip-crit " . criticalcooling-mapsmap0 90 > cpu4-thermal   tripstrip-alert "L .passivetrip-crit " . criticalcooling-mapsmap0 90 > cpu5-thermal   tripstrip-alert "L .passivetrip-crit " . criticalcooling-mapsmap0 90 > cpu6-thermal   tripstrip-alert "L .passivetrip-crit " . criticalcooling-mapsmap0 90 > cpu7-thermal   tripstrip-alert "L .passivetrip-crit " . criticalcooling-mapsmap0 90 > vpu0-thermal   tripstrip-alert "L .passivetrip-crit " . criticalvpu1-thermal    tripstrip-alert "L .passivetrip-crit " . criticalgpu-thermal    tripstrip-alert "L .passivetrip-crit " . criticalgpu1-thermal    tripstrip-alert "L .passivetrip-crit " . criticalvdec-thermal    tripstrip-alert "L .passivetrip-crit " . criticalimg-thermal    tripstrip-alert "L .passivetrip-crit " . criticalinfra-thermal   tripstrip-alert "L .passivetrip-crit " . criticalcam0-thermal   tripstrip-alert "L .passivetrip-crit " . criticalcam1-thermal   tripstrip-alert "L .passivetrip-crit " . criticalchosen Mserial0:921600n8firmwareopteelinaro,optee-tzsmcgpio-keys gpio-keysdefaultkey-0 Zj Yvolume_up _s{ jmemory@40000000memory@reserved-memory+optee@43200000 |C memory@50000000shared-dma-poolP |memory@53000000shared-dma-poolS@memory@54600000 |T` memory@60000000shared-dma-pool` |memory@62000000shared-dma-poolb@ compatibleinterrupt-parent#address-cells#size-cellsmodeldp-intf0dp-intf1gce0gce1ethdr0mutex0mutex1merge1merge2merge3merge4merge5vdo1-rdma0vdo1-rdma1vdo1-rdma2vdo1-rdma3vdo1-rdma4vdo1-rdma5vdo1-rdma6vdo1-rdma7serial0device_typeregenable-methodperformance-domainsclock-frequencycapacity-dmips-mhzcpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cache#cooling-cellsphandlecpuentry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedinterruptscpusstatusnum-channelswakeup-delay-msmediatek,platform#clock-cellsclocksclock-divclock-multclock-output-names#performance-domain-cellsopp-sharedopp-hzopp-microvoltrangesdma-ranges#interrupt-cells#redistributor-regionsinterrupt-controlleraffinity#reset-cellsreg-namesgpio-controller#gpio-cellsgpio-rangespinmuxdrive-strengthinput-enableoutput-highinput-disablebias-disablebias-pull-upbias-pull-down#power-domain-cellsclock-namesmediatek,infracfgmediatek,disable-extrstassigned-clocksassigned-clock-parentsinterrupts-extended#io-channel-cellsregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-enable-ramp-delayregulator-always-onregulator-ramp-delayregulator-allowed-modes#iommu-cells#mbox-cellspower-domainsmbox-namesmboxesmediatek,topckgenresetsreset-namespinctrl-namespinctrl-0nvmem-cellsnvmem-cell-names#thermal-sensor-cells#pwm-cellsinterrupt-namesmediatek,pericfgsnps,axi-configsnps,mtl-rx-configsnps,mtl-tx-configsnps,txpblsnps,rxpblsnps,clk-csrphy-modephy-handlesnps,reset-gpiosnps,reset-delays-uspinctrl-1snps,wr_osr_lmtsnps,rd_osr_lmtsnps,blensnps,rx-queues-to-usesnps,rx-sched-spsnps,dcb-algorithmsnps,map-to-dma-channelsnps,tx-queues-to-usesnps,tx-sched-wrrsnps,weightsnps,priorityphyswakeup-sourcemediatek,syscon-wakeupvusb33-supplyvbus-supplybus-widthmax-frequencycap-mmc-highspeedmmc-hs200-1_8vmmc-hs400-1_8vcap-mmc-hw-resetno-sdiono-sdhs400-ds-delayvmmc-supplyvqmmc-supplynon-removablecd-gpioscap-sd-highspeedsd-uhs-sdr50sd-uhs-sdr104bus-rangeiommu-mapiommu-map-maskphy-namesinterrupt-map-maskinterrupt-mapbits#phy-cellsrichtek,vinovp-microvoltLDO_VIN3-supplyoperating-points-v2power-domain-namesmediatek,gce-client-regmediatek,gce-eventsmediatek,scpiommus#dma-cellsmediatek,smimediatek,larb-idmediatek,larbsmediatek,merge-mutemediatek,merge-fifo-enmax-linkrate-mhzpolling-delaypolling-delay-passivethermal-sensorstemperaturehysteresistripcooling-devicestdout-pathlabellinux,codedebounce-intervalno-map