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#address-cells#size-cellsmodelcompatibleinterrupt-parentrangesregno-mapphandleenable-methoddevice_typenext-level-cacheqcom,accqcom,sawcpu-idle-statescache-levelcache-unifiedentry-latency-usexit-latency-usmin-residency-uspolling-delay-passivepolling-delaythermal-sensorscoefficientstemperaturehysteresisinterrupts#clock-cellsclock-frequencysyscon#hwlock-cellsmemory-regionhwlocksqcom,ipc-1qcom,ipc-2qcom,ipc-3qcom,ipc-4#qcom,smem-state-cellsinterrupt-controller#interrupt-cellsclocksclock-namesgpio-controllergpio-ranges#gpio-cellspinctrl-namespinctrl-0pinsdrive-strengthbias-disablebias-pull-upfunctionoutput-highbias-pull-downcpu-offsetclock-output-namesregulator-min-microvoltregulator-max-microvoltstatuscell-indexsyscon-tcsrqcom,modepinctrl-1pagesizenum-cscs-gpiosqcom,controller-typeinterrupts-extendeddebounceallow-set-timescan-delayrow-holdpower-source#io-channel-cells#reset-cellsnvmem-cellsnvmem-cell-namesinterrupt-names#qcom,sensors#thermal-sensor-cells#power-domain-cellsqcom,ipcvin_lvs1_3_6-supplyvin_lvs2-supplyvin_lvs4_5_7-supplyvdd_l1_l2_l12_l18-supplyvdd_l24-supplyvdd_l25-supplyvdd_l26-supplyvdd_l27-supplyvdd_l28-supplyregulator-always-onqcom,switch-mode-frequencyassigned-clocksassigned-clock-ratesresetsreset-namesphy_typeahb-burst-configphysphy-namesdr_mode#phy-cellsv3p3-supplyv1p8-supplyports-implementedtarget-supplyarm,primecell-periphidbus-widthcap-sd-highspeedcap-mmc-highspeedmax-frequencyno-1-8-vdmasdma-namesvmmc-supplycd-gpios#dma-cellsqcom,eevqmmc-supplymmc-pwrseqnon-removablereg-namesiommusoperating-points-v2opp-hzassigned-clock-parentssyscon-sfpb#iommu-cellsqcom,ncblinux,pci-domainbus-rangenum-lanesinterrupt-map-maskinterrupt-mapvdda-supplyvdda_phy-supplyvdda_refclk-supplyperst-gpioscore-vdda-supplyhpd-gpiosremote-endpointqcom,smd-edgelabelqcom,smd-channelsqcom,mmioqcom,smem-statesqcom,smem-state-namescpuio-channelsserial0serial1i2c0i2c1i2c2i2c3spi0stdout-pathcolordefault-statereset-gpiosregulator-namestartup-delay-usgpioenable-active-highregulator-boot-on