� �� 18�( e�Pgumstix,omap3-overo-alto35gumstix,omap3-overoti,omap3630ti,omap36xxti,omap3 +/7OMAP36xx/AM37xx/DM37xx Gumstix Overo on Alto35chosenaliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/mmc@4809c000Q/ocp@68000000/mmc@480b4000V/ocp@68000000/mmc@480ad000[/ocp@68000000/serial@4806a000c/ocp@68000000/serial@4806c000k/ocp@68000000/serial@49020000s/ocp@68000000/serial@49042000%{/ocp@68000000/spi@48098000/display@1cpus+cpu@0arm,cortex-a8�cpu���cpu�������pmu@54000000arm,cortex-a8-pmu�T���debugsssocti,omap-inframpu ti,omap3-mpu�mpuiva ti,iva2.2�ivadsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-bus�h� +�l3_mainl4@48000000ti,omap3-l4-coresimple-bus+ Hscm@2000ti,omap3-scmsimple-bus� +  pinmux@30 ti,omap3-padconfpinctrl-single�08+'<Z�wdefault���pinmux_uart2_pins �<>@B��pinmux_i2c1_pins�����pinmux_mmc1_pins0���pinmux_mmc2_pins0�(*,.02��pinmux_w3cbw003c_pins��l�pinmux_hsusb2_pins@�� � � � � � ���pinmux_twl4030_pins��A��pinmux_i2c3_pins�����pinmux_uart3_pins�np��pinmux_dss_dpi_pins������������������������������� pinmux_lb035_pins�D��pinmux_backlight_pins�F�!pinmux_mcspi1_pins(��������pinmux_ads7846_pins� ��pinmux_led_pins �LPR��"scm_conf@270sysconsimple-bus�p0+ p0�pbias_regulator@2b0ti,pbias-omap3ti,pbias-omap���pbias_mmc_omap2430�pbias_mmc_omap2430�w@�-����clocks+mcbsp5_mux_fck@68�ti,composite-mux-clock���h� mcbsp5_fck�ti,composite-clock� �mcbsp1_mux_fck@4�ti,composite-mux-clock���� mcbsp1_fck�ti,composite-clock� �mcbsp2_mux_fck@4�ti,composite-mux-clock� ���mcbsp2_fck�ti,composite-clock��mcbsp3_mux_fck@68�ti,composite-mux-clock� �h�mcbsp3_fck�ti,composite-clock��mcbsp4_mux_fck@68�ti,composite-mux-clock� ��h�mcbsp4_fck�ti,composite-clock��clockdomainspinmux@a00 ti,omap3-padconfpinctrl-single� \+'<Z�pinmux_twl4030_vpins ���pinmux_button_pins��#target-module@480a6000ti,sysc-omap2ti,sysc�H `DH `HH `Lrevsyscsyss  (��ick+ H ` aes1@0 ti,omap3-aes�P�5  :txrxtarget-module@480c5000ti,sysc-omap2ti,sysc�H PDH PHH PLrevsyscsyss  (��ick+ H P aes2@0 ti,omap3-aes�P�5AB:txrxprm@48306000 ti,omap3-prm�H0`@� clocks+virt_16_8m_ck� fixed-clockDY�osc_sys_ck@d40� ti,mux-clock�� @�sys_ck@1270�ti,divider-clock��T�p_�"sys_clkout1@d70�ti,gate-clock�� p�dpll3_x2_ck�fixed-factor-clock�v�dpll3_m2x2_ck�fixed-factor-clock�v��!dpll4_x2_ck�fixed-factor-clock� v�corex2_fck�fixed-factor-clock�!v��#wkup_l4_ick�fixed-factor-clock�"v��Rcorex2_d3_fck�fixed-factor-clock�#v���corex2_d5_fck�fixed-factor-clock�#v���clockdomainscm@48004000 ti,omap3-cm�H@@clocks+dummy_apb_pclk� fixed-clockDomap_32k_fck� fixed-clockD��Dvirt_12m_ck� fixed-clockD��virt_13m_ck� fixed-clockD�]@�virt_19200000_ck� fixed-clockD$��virt_26000000_ck� fixed-clockD����virt_38_4m_ck� fixed-clockDI��dpll4_ck@d00�ti,omap3-dpll-per-j-type-clock�""� D 0� dpll4_m2_ck@d48�ti,divider-clock� T?� H_�$dpll4_m2x2_mul_ck�fixed-factor-clock�$v��%dpll4_m2x2_ck@d00�ti,hsdiv-gate-clock�%�� ��&omap_96m_alwon_fck�fixed-factor-clock�&v��-dpll3_ck@d00�ti,omap3-dpll-core-clock�""� @ 0�dpll3_m3_ck@1140�ti,divider-clock��T�@_�'dpll3_m3x2_mul_ck�fixed-factor-clock�'v��(dpll3_m3x2_ck@d00�ti,hsdiv-gate-clock�(� � ��)emu_core_alwon_ck�fixed-factor-clock�)v��fsys_altclk� fixed-clockD�2mcbsp_clks� fixed-clockD�dpll3_m2_ck@d40�ti,divider-clock��T� @_�core_ck�fixed-factor-clock�v��*dpll1_fck@940�ti,divider-clock�*�T� @_�+dpll1_ck@904�ti,omap3-dpll-clock�"+�  $ @ 4�dpll1_x2_ck�fixed-factor-clock�v��,dpll1_x2m2_ck@944�ti,divider-clock�,T� D_�@cm_96m_fck�fixed-factor-clock�-v��.omap_96m_fck@d40� ti,mux-clock�."�� @�Idpll4_m3_ck@e40�ti,divider-clock� �T �@_�/dpll4_m3x2_mul_ck�fixed-factor-clock�/v��0dpll4_m3x2_ck@d00�ti,hsdiv-gate-clock�0�� ��1omap_54m_fck@d40� ti,mux-clock�12�� @�<cm_96m_d2_fck�fixed-factor-clock�.v��3omap_48m_fck@d40� ti,mux-clock�32�� @�4omap_12m_fck�fixed-factor-clock�4v��Kdpll4_m4_ck@e40�ti,divider-clock� T�@_�5dpll4_m4x2_mul_ck�ti,fixed-factor-clock�5����6dpll4_m4x2_ck@d00�ti,gate-clock�6�� ����dpll4_m5_ck@f40�ti,divider-clock� T?�@_�7dpll4_m5x2_mul_ck�ti,fixed-factor-clock�7����8dpll4_m5x2_ck@d00�ti,hsdiv-gate-clock�8�� ���ndpll4_m6_ck@1140�ti,divider-clock� �T?�@_�9dpll4_m6x2_mul_ck�fixed-factor-clock�9v��:dpll4_m6x2_ck@d00�ti,hsdiv-gate-clock�:�� ��;emu_per_alwon_ck�fixed-factor-clock�;v��gclkout2_src_gate_ck@d70� ti,composite-no-wait-gate-clock�*�� p�=clkout2_src_mux_ck@d70�ti,composite-mux-clock�*".<� p�>clkout2_src_ck�ti,composite-clock�=>�?sys_clkout2@d70�ti,divider-clock�?�T@� p�mpu_ck�fixed-factor-clock�@v��Aarm_fck@924�ti,divider-clock�A� $Temu_mpu_alwon_ck�fixed-factor-clock�Av��hl3_ick@a40�ti,divider-clock�*T� @_�Bl4_ick@a40�ti,divider-clock�B�T� @_�Crm_ick@c40�ti,divider-clock�C�T� @_gpt10_gate_fck@a00�ti,composite-gate-clock�"� � �Egpt10_mux_fck@a40�ti,composite-mux-clock�D"�� @�Fgpt10_fck�ti,composite-clock�EFgpt11_gate_fck@a00�ti,composite-gate-clock�"� � �Ggpt11_mux_fck@a40�ti,composite-mux-clock�D"�� @�Hgpt11_fck�ti,composite-clock�GHcore_96m_fck�fixed-factor-clock�Iv��mmchs2_fck@a00�ti,wait-gate-clock�� ���mmchs1_fck@a00�ti,wait-gate-clock�� ���i2c3_fck@a00�ti,wait-gate-clock�� ���i2c2_fck@a00�ti,wait-gate-clock�� ���i2c1_fck@a00�ti,wait-gate-clock�� ���mcbsp5_gate_fck@a00�ti,composite-gate-clock�� � � mcbsp1_gate_fck@a00�ti,composite-gate-clock�� � � core_48m_fck�fixed-factor-clock�4v��Jmcspi4_fck@a00�ti,wait-gate-clock�J� ���mcspi3_fck@a00�ti,wait-gate-clock�J� ���mcspi2_fck@a00�ti,wait-gate-clock�J� ���mcspi1_fck@a00�ti,wait-gate-clock�J� ���uart2_fck@a00�ti,wait-gate-clock�J� ���uart1_fck@a00�ti,wait-gate-clock�J� � ��core_12m_fck�fixed-factor-clock�Kv��Lhdq_fck@a00�ti,wait-gate-clock�L� ���core_l3_ick�fixed-factor-clock�Bv��Msdrc_ick@a10�ti,wait-gate-clock�M� ���gpmc_fck�fixed-factor-clock�Mv�core_l4_ick�fixed-factor-clock�Cv��Nmmchs2_ick@a10�ti,omap3-interface-clock�N� ���mmchs1_ick@a10�ti,omap3-interface-clock�N� ���hdq_ick@a10�ti,omap3-interface-clock�N� ���mcspi4_ick@a10�ti,omap3-interface-clock�N� ���mcspi3_ick@a10�ti,omap3-interface-clock�N� ���mcspi2_ick@a10�ti,omap3-interface-clock�N� ���mcspi1_ick@a10�ti,omap3-interface-clock�N� ���i2c3_ick@a10�ti,omap3-interface-clock�N� ���i2c2_ick@a10�ti,omap3-interface-clock�N� ���i2c1_ick@a10�ti,omap3-interface-clock�N� ���uart2_ick@a10�ti,omap3-interface-clock�N� ���uart1_ick@a10�ti,omap3-interface-clock�N� � ��gpt11_ick@a10�ti,omap3-interface-clock�N� � ��gpt10_ick@a10�ti,omap3-interface-clock�N� � ��mcbsp5_ick@a10�ti,omap3-interface-clock�N� � ��mcbsp1_ick@a10�ti,omap3-interface-clock�N� � ��omapctrl_ick@a10�ti,omap3-interface-clock�N� ���dss_tv_fck@e00�ti,gate-clock�<����dss_96m_fck@e00�ti,gate-clock�I����dss2_alwon_fck@e00�ti,gate-clock�"����dummy_ck� fixed-clockDgpt1_gate_fck@c00�ti,composite-gate-clock�"�� �Ogpt1_mux_fck@c40�ti,composite-mux-clock�D"� @�Pgpt1_fck�ti,composite-clock�OP�aes2_ick@a10�ti,omap3-interface-clock�N�� �wkup_32k_fck�fixed-factor-clock�Dv��Qgpio1_dbck@c00�ti,gate-clock�Q� ���sha12_ick@a10�ti,omap3-interface-clock�N� ���wdt2_fck@c00�ti,wait-gate-clock�Q� ���wdt2_ick@c10�ti,omap3-interface-clock�R� ���wdt1_ick@c10�ti,omap3-interface-clock�R� ���gpio1_ick@c10�ti,omap3-interface-clock�R� ���omap_32ksync_ick@c10�ti,omap3-interface-clock�R� ���gpt12_ick@c10�ti,omap3-interface-clock�R� ���gpt1_ick@c10�ti,omap3-interface-clock�R� ���per_96m_fck�fixed-factor-clock�-v�� per_48m_fck�fixed-factor-clock�4v��Suart3_fck@1000�ti,wait-gate-clock�S�� ��gpt2_gate_fck@1000�ti,composite-gate-clock�"���Tgpt2_mux_fck@1040�ti,composite-mux-clock�D"�@�Ugpt2_fck�ti,composite-clock�TU�gpt3_gate_fck@1000�ti,composite-gate-clock�"���Vgpt3_mux_fck@1040�ti,composite-mux-clock�D"��@�Wgpt3_fck�ti,composite-clock�VWgpt4_gate_fck@1000�ti,composite-gate-clock�"���Xgpt4_mux_fck@1040�ti,composite-mux-clock�D"��@�Ygpt4_fck�ti,composite-clock�XYgpt5_gate_fck@1000�ti,composite-gate-clock�"���Zgpt5_mux_fck@1040�ti,composite-mux-clock�D"��@�[gpt5_fck�ti,composite-clock�Z[gpt6_gate_fck@1000�ti,composite-gate-clock�"���\gpt6_mux_fck@1040�ti,composite-mux-clock�D"��@�]gpt6_fck�ti,composite-clock�\]gpt7_gate_fck@1000�ti,composite-gate-clock�"���^gpt7_mux_fck@1040�ti,composite-mux-clock�D"��@�_gpt7_fck�ti,composite-clock�^_gpt8_gate_fck@1000�ti,composite-gate-clock�"� ��`gpt8_mux_fck@1040�ti,composite-mux-clock�D"��@�agpt8_fck�ti,composite-clock�`agpt9_gate_fck@1000�ti,composite-gate-clock�"� ��bgpt9_mux_fck@1040�ti,composite-mux-clock�D"��@�cgpt9_fck�ti,composite-clock�bcper_32k_alwon_fck�fixed-factor-clock�Dv��dgpio6_dbck@1000�ti,gate-clock�d����gpio5_dbck@1000�ti,gate-clock�d����gpio4_dbck@1000�ti,gate-clock�d����gpio3_dbck@1000�ti,gate-clock�d����gpio2_dbck@1000�ti,gate-clock�d�� ��wdt3_fck@1000�ti,wait-gate-clock�d�� ��per_l4_ick�fixed-factor-clock�Cv��egpio6_ick@1010�ti,omap3-interface-clock�e����gpio5_ick@1010�ti,omap3-interface-clock�e����gpio4_ick@1010�ti,omap3-interface-clock�e����gpio3_ick@1010�ti,omap3-interface-clock�e����gpio2_ick@1010�ti,omap3-interface-clock�e�� ��wdt3_ick@1010�ti,omap3-interface-clock�e�� ��uart3_ick@1010�ti,omap3-interface-clock�e�� ��uart4_ick@1010�ti,omap3-interface-clock�e����gpt9_ick@1010�ti,omap3-interface-clock�e�� ��gpt8_ick@1010�ti,omap3-interface-clock�e�� ��gpt7_ick@1010�ti,omap3-interface-clock�e����gpt6_ick@1010�ti,omap3-interface-clock�e����gpt5_ick@1010�ti,omap3-interface-clock�e����gpt4_ick@1010�ti,omap3-interface-clock�e����gpt3_ick@1010�ti,omap3-interface-clock�e����gpt2_ick@1010�ti,omap3-interface-clock�e����mcbsp2_ick@1010�ti,omap3-interface-clock�e����mcbsp3_ick@1010�ti,omap3-interface-clock�e����mcbsp4_ick@1010�ti,omap3-interface-clock�e����mcbsp2_gate_fck@1000�ti,composite-gate-clock����mcbsp3_gate_fck@1000�ti,composite-gate-clock����mcbsp4_gate_fck@1000�ti,composite-gate-clock����emu_src_mux_ck@1140� ti,mux-clock�"fgh�@�iemu_src_ck�ti,clkdm-gate-clock�i�jpclk_fck@1140�ti,divider-clock�j�T�@_pclkx2_fck@1140�ti,divider-clock�j�T�@_atclk_fck@1140�ti,divider-clock�j�T�@_traceclk_src_fck@1140� ti,mux-clock�"fgh��@�ktraceclk_fck@1140�ti,divider-clock�k� T�@_secure_32k_fck� fixed-clockD��lgpt12_fck�fixed-factor-clock�lv�� wdt1_fck�fixed-factor-clock�lv�security_l4_ick2�fixed-factor-clock�Cv��maes1_ick@a14�ti,omap3-interface-clock�m�� �rng_ick@a14�ti,omap3-interface-clock�m� ��sha11_ick@a14�ti,omap3-interface-clock�m� �des1_ick@a14�ti,omap3-interface-clock�m� �cam_mclk@f00�ti,gate-clock�n���cam_ick@f10�!ti,omap3-no-wait-interface-clock�C����csi2_96m_fck@f00�ti,gate-clock�����security_l3_ick�fixed-factor-clock�Bv��opka_ick@a14�ti,omap3-interface-clock�o� �icr_ick@a10�ti,omap3-interface-clock�N� �des2_ick@a10�ti,omap3-interface-clock�N� �mspro_ick@a10�ti,omap3-interface-clock�N� �mailboxes_ick@a10�ti,omap3-interface-clock�N� �ssi_l4_ick�fixed-factor-clock�Cv��vsr1_fck@c00�ti,wait-gate-clock�"� ��sr2_fck@c00�ti,wait-gate-clock�"� ��sr_l4_ick�fixed-factor-clock�Cv�dpll2_fck@40�ti,divider-clock�*�T�@_�pdpll2_ck@4�ti,omap3-dpll-clock�"p�$@4����qdpll2_m2_ck@44�ti,divider-clock�qT�D_�riva2_ck@0�ti,wait-gate-clock�r����modem_fck@a00�ti,omap3-interface-clock�"� ���sad2d_ick@a10�ti,omap3-interface-clock�B� ���mad2d_ick@a18�ti,omap3-interface-clock�B� ���mspro_fck@a00�ti,wait-gate-clock�� �ssi_ssr_gate_fck_3430es2@a00� ti,composite-no-wait-gate-clock�#�� �sssi_ssr_div_fck_3430es2@a40�ti,composite-divider-clock�#�� @$�tssi_ssr_fck_3430es2�ti,composite-clock�st�ussi_sst_fck_3430es2�fixed-factor-clock�uv��hsotgusb_ick_3430es2@a10�"ti,omap3-hsotgusb-interface-clock�M� ���ssi_ick_3430es2@a10�ti,omap3-ssi-interface-clock�v� ��usim_gate_fck@c00�ti,composite-gate-clock�I� � ��sys_d2_ck�fixed-factor-clock�"v��xomap_96m_d2_fck�fixed-factor-clock�Iv��yomap_96m_d4_fck�fixed-factor-clock�Iv��zomap_96m_d8_fck�fixed-factor-clock�Iv��{omap_96m_d10_fck�fixed-factor-clock�Iv� �|dpll5_m2_d4_ck�fixed-factor-clock�wv��}dpll5_m2_d8_ck�fixed-factor-clock�wv��~dpll5_m2_d16_ck�fixed-factor-clock�wv��dpll5_m2_d20_ck�fixed-factor-clock�wv���usim_mux_fck@c40�ti,composite-mux-clock(�"xyz{|}~��� @_��usim_fck�ti,composite-clock���usim_ick@c10�ti,omap3-interface-clock�R� � ��dpll5_ck@d04�ti,omap3-dpll-clock�""�  $ L 4����dpll5_m2_ck@d50�ti,divider-clock��T� P_�wsgx_gate_fck@b00�ti,composite-gate-clock�*�� ��core_d3_ck�fixed-factor-clock�*v���core_d4_ck�fixed-factor-clock�*v���core_d6_ck�fixed-factor-clock�*v���omap_192m_alwon_fck�fixed-factor-clock�&v���core_d2_ck�fixed-factor-clock�*v���sgx_mux_fck@b40�ti,composite-mux-clock ����.����� @��sgx_fck�ti,composite-clock����sgx_ick@b10�ti,wait-gate-clock�B� ���cpefuse_fck@a08�ti,gate-clock�"� ���ts_fck@a08�ti,gate-clock�D� ���usbtll_fck@a08�ti,wait-gate-clock�w� ���usbtll_ick@a18�ti,omap3-interface-clock�N� ���mmchs3_ick@a10�ti,omap3-interface-clock�N� ���mmchs3_fck@a00�ti,wait-gate-clock�� ���dss1_alwon_fck_3430es2@e00�ti,dss-gate-clock�������dss_ick_3430es2@e10�ti,omap3-dss-interface-clock�C����usbhost_120m_fck@1400�ti,gate-clock�w����usbhost_48m_fck@1400�ti,dss-gate-clock�4����usbhost_ick@1410�ti,omap3-dss-interface-clock�C����uart4_fck@1000�ti,wait-gate-clock�S����clockdomainscore_l3_clkdmti,clockdomain���dpll3_clkdmti,clockdomain�dpll1_clkdmti,clockdomain�per_clkdmti,clockdomainl����������������������������emu_clkdmti,clockdomain�jdpll4_clkdmti,clockdomain� wkup_clkdmti,clockdomain$����������dss_clkdmti,clockdomain������core_l4_clkdmti,clockdomain��������������������������������������cam_clkdmti,clockdomain���iva2_clkdmti,clockdomain��dpll2_clkdmti,clockdomain�qd2d_clkdmti,clockdomain ����dpll5_clkdmti,clockdomain��sgx_clkdmti,clockdomain��usbhost_clkdmti,clockdomain ����target-module@48320000ti,sysc-omap2ti,sysc�H2H2 revsysc�Q��fckick+ H2counter@0ti,omap-counter32k� interrupt-controller@48200000ti,omap3-intc'�H �target-module@48056000ti,sysc-omap2ti,sysc�H`H`,H`(revsyscsyss #  (�M�ick+ H`dma-controller@0ti,omap3630-sdmati,omap-sdma�� -8 E`�gpio@48310000ti,omap3-gpio�H1��gpio1Rdt'� gpio@49050000ti,omap3-gpio�I��gpio2dt'�gpio@49052000ti,omap3-gpio�I ��gpio3dt'gpio@49054000ti,omap3-gpio�I@� �gpio4dt'��gpio@49056000ti,omap3-gpio�I`�!�gpio5dt'��gpio@49058000ti,omap3-gpio�I��"�gpio6dt'�serial@4806a000ti,omap3-uart�H� �H512:txrx�uart1D�lserial@4806c000ti,omap3-uart�H��I534:txrx�uart2D�lwdefault��serial@49020000ti,omap3-uart�I�J�n556:txrx�uart3D�lwdefault��i2c@48070000 ti,omap3-i2c�H��85:txrx+�i2c1wdefault��D'�@twl@48�H�  ti,twl4030'wdefault���audioti,twl4030-audiocodecrtcti,twl4030-rtc� bciti,twl4030-bci� ���� �vacwatchdogti,twl4030-wdtregulator-vaux1ti,twl4030-vaux1regulator-vaux2ti,twl4030-vaux2regulator-vaux3ti,twl4030-vaux3regulator-vaux4ti,twl4030-vaux4regulator-vdd1ti,twl4030-vdd1� '�� regulator-vdacti,twl4030-vdac�w@�w@regulator-vioti,twl4030-vioregulator-vintana1ti,twl4030-vintana1regulator-vintana2ti,twl4030-vintana2regulator-vintdigti,twl4030-vintdigregulator-vmmc1ti,twl4030-vmmc1�:��0���regulator-vmmc2ti,twl4030-vmmc2�:��0�regulator-vusb1v5ti,twl4030-vusb1v5��regulator-vusb1v8ti,twl4030-vusb1v8��regulator-vusb3v1ti,twl4030-vusb3v1��regulator-vpll1ti,twl4030-vpll1regulator-vpll2ti,twl4030-vpll2�w@�w@�regulator-vsimti,twl4030-vsim�w@�-��gpioti,twl4030-gpiodt'�twl4030-usbti,twl4030-usb� ������ � pwmti,twl4030-pwmpwmledti,twl4030-pwmled�pwrbuttonti,twl4030-pwrbutton�keypadti,twl4030-keypad�(8madcti,twl4030-madc�K��i2c@48072000 ti,omap3-i2c�H ��95:txrx+�i2c2 ]disabledi2c@48060000 ti,omap3-i2c�H��=5:txrx+�i2c3wdefault��D��eeprom@51 atmel,24c01�Qdlis33de@1dst,lis33dest,lis3lv02d�m�x����� � � �,;JYhxwx���&�&��mailbox@48094000ti,omap3-mailbox�mailbox�H @����dsp � �spi@48098000ti,omap2-mcspi�H ��A+�mcspi1@5#$%&'()* :tx0rx0tx1rx1tx2rx2tx3rx3wdefault��display@1lgphilips,lb035q02lcd35�� .7wdefault�� @�portendpointM��ads7846@0wdefault�� ti,ads7846]���` �� h�u~���������spi@4809a000ti,omap2-mcspi�H ��B+�mcspi2 5+,-.:tx0rx0tx1rx1spi@480b8000ti,omap2-mcspi�H ��[+�mcspi3 5:tx0rx0tx1rx1spi@480ba000ti,omap2-mcspi�H ��0+�mcspi45FG:tx0rx01w@480b2000 ti,omap3-1w�H �:�hdq1wmmc@4809c000ti,omap3-hsmmc�H ��S�mmc1�5=>:txrx��wdefault�����mmc@480b4000ti,omap3-hsmmc�H @�V�mmc25/0:txrxwdefault������mmc@480ad000ti,omap3-hsmmc�H ��^�mmc35MN:txrx ]disabledmmu@480bd400ti,omap2-iommu�H ����mmu_isp,�mmu@5d000000ti,omap2-iommu�]���mmu_iva ]disabledwdt@48314000 ti,omap3-wdt�H1@� �wd_timer2mcbsp@48074000ti,omap3-mcbsp�H@�mpu �;< ?