The functional characterization of a cone is computed from the branch structure. A Boolean expression is generated for all the branches leading to Vdd. It gives the set condition of the node. Another expression is constructed for all the branches leading to Vss. It gives the reset condition of the node.
Each branch is considered as a chain of switches. For a N-Channel transistor, the switch is off when the gate signal is high. For a P-Channel transistor, the switch is off when the gate signal is low.
For the signal E, the set condition is Eup, the reset condition is Edn. With those two expressions, it is possible to analyze the functionality of the cone. We must verify their orthogonality and their completeness.
If the two expressions are orthogonal, it exists no combination of the inputs for which a Vdd branch is active simultaneously as a Vss branch, i.e. if Eup+Edn = 0, the cone is non-conflictual. If the two expressions are complete, it exists no combination of the inputs for which no branch is active, i.e. if Eup+Edn = 1, the cone is non-HZ.
A cone that respects the orthogonality and completeness conditions is said to be CMOS DUAL.
For example, as Eup and Edn respect those conditions, they can then be grouped into a single expression on E: E = not C or not B
Cup and Cdn do not respect orthogonality and completeness conditions, then the up and down conditions remain separated.
The timing characterization of a cone is also computed from the branch structure, and then it perfectly maps on the functional characterization. Let's take the cone E of the following figure as an example.
A propagation time is associated to a couple of signals: the output E of the cone, and one of its inputs (C or D). Actually, the switching of C or D does not always lead to the switching of E: the rising of C leads to the falling of E only if D has the logical value 1.
The computation of the propagation time CE is made under the hypothesis that the switching of the E is induced par the switching of C.
The value of the propagation time is then computed by a mixed analytical-numerical method, based on the IV curves and capacitances of the MOS transistors BSIM3/BSIM4 technology models.
Each possible propagation of a input transition towards a transition on the output is characterized; the cones are then characterized as follow:
The VHDL|Verilog characterization is done by translating the behavioral models of the cones into VHDL|Verilog syntax:
For CMOS DUAL cones, a single signal assignment is generated, for example for the cone E as demonstrated in the first column (left), for non-CMOS DUAL cones, a process is built, listing all the possible assignations as it can be seen in the second column (right).
The final VHDL|Verilog is generated by mapping the timing characterization on the functional characterization.
For CMOS DUAL cones, three levels of precision are available. Let's take the cone E as an example: in term of behavior, the reduction of the expressions Eup and Edn to a single expression E = not C or not D is lossless. It is not the case in terms of timing: there are different timings associated with each expression and with each event occurring on a variable of the expression.
First level of precision:
If we intend to keep a compact VHDL|Verilog (i.e. the expression E = not C or not D), we must choose one timing among all the different timings characterizing the cone E. Typically, in Yagle, it is possible to choose between the maximum timing, the minimum timing, and the average timing. With choosing the maximum timing, this first level of precision leads to the following expression:
Second level of precision:
Second and third levels of precision are obtained through splitting the expression E into Eup and Edn expressions. The second level of precision does not take into account the events on the variables of the expressions. The maximum, minimum or average timing can be chosen for up and down expression.
With choosing the maximum timing, this second level of precision leads to the following expression:
Third level of precision:
The third level performs the complete timing characterization of the cone. A timing is associated with each event of each variable of each expression of the cone:
For non-CMOS DUAL cones, as the up and down expressions are not reduced to a single expression, only the second and third levels of precision are available.