4. Configuration Variables

4. 1. License Server

avtLicenseServer

<string> Hostname of the machine running the license server

avtLicenseProject

<string> Project name. Used in license logging.

4. 2. Environment

avtLibraryDirs

<string> The set of library directories which are scanned for required subcircuits.

avtBlackboxFile

<string> Name of the file containing the cells to exclude of analysis.

avtCatalogueName

<string> File containing a list of subcircuits to be considered as leaf cells when flattening a design. Each line in this file refers to a single subcircuit, with the format <subcircuit> C. The default value is CATAL.

4. 3. Log File and Error Policy

avtErrorPolicy

lenient Default, the tool does not abort when encountering an error of level 1 (level 0 is WARNING, level 1 is ERROR, level 2 is FATAL ERROR).
strict the tool aborts when encountering an error of level 2.

avtLogFile

<string> Name of the log file. If this variable is not set, no log file will be created (default behavior).

avtLogEnable
Enables the logging of the different steps of the timing analysis process. The syntax is as follow:

avtLogEnable "step:level"

the step parameter can take one or more of the following values:

files info related to file access: FAC and MCH sections
spice info related to spice netlist and technology file parser: SPI section
mos_charac info related to MOSFET characterization: MCC section
rc info related to RC networs processing: RCN and TRC sections
disassembly info related to transistor netlist partitioning: YAG section
delay_calc info related to delay calculation: TAS and STM sections
spicedeck info related to spice deck generation: EFG and GSP sections
timing_abs info related to timing abstraction: LIB and TLF sections
error redirection of errors in the log file: ERR section
stat info related to netlist parse: PRS section
config info related to configuration avttools.conf and information files
stability info related to stability: STABILITY section

The level value ranges from 0 to 9. Level 0 is stdout redirection, level 1 is customer info, levels 2 to 9 are debugging levels.

Example:

avtLogEnable "files:1 mos_charac:1

avtWarningFilter

<string> Allows the filtering of warning messages on stdout and in the log file. Specify a list of error message identifiers for the messges to be filtered

Example:

avtWarningFilter "SPF-003 SPF-015"

4. 4. Names

avtVddName

<string> Name of any signal or connector which is to be considered as power supply (a * in the name matches any string). Several names, separated by :, may be specified.

avtVssName

<string> Name of any signal or connector which is to be considered as ground (a * in the name matches any string). Several names, separated by :, may be specified.

avtGlobalVddName

<string> Name of an internal signal to be considered as power supply (a * in the name matches any string). Signals in different subcircuits of a hierarchical netlist with a name given here will be considered as equipotential and this name will be used in the flattened netlist. This is identical to the use of the .GLOBAL directive in a spice netlist. Several names, separated by :, may be specified.

avtGlobalVssName

<string> Name of an internal signal to be considered as ground (a * in the name matches any string). Signals in different subcircuits of a hierarchical netlist with a name given here will be considered as equipotential and this name will be used in the flattened netlist. This is identical to the use of the .GLOBAL directive in a spice netlist. Several names, separated by :, may be specified.

avtCaseSensitive

yes Upper and lower case characters are distinct
no Upper and lower case characters are seen as identical
preserve Default, upper and lower case characters are seen as identical but the original case is preserved

avtInstanceSeparator

<char> Character used to separate instance names in a hierarchical description. Default value is .

avtFlattenKeepsAllSignalNames

yes When flattening a netlist, each signal keeps all its names through the hierarchy.
no Default, only one name (the shortest) is kept per signal.

avtVectorize
Controls the internal representation of vector-signals.

yes Default, vector-signals are represented internally as vectors, as far as the vector indexation is one of [], <>, _. For example, if both foo[1], foo<1> and foo_1 appear in the source file, they will all be represented internally as foo 1
no Vector signals are represented internally as they appear in the source file.
<string> Explicits the vector-signals indexations that will be interpreted as vectors, and the represented internally as vectors. string is a comma-separated list of single or paired delimiters. For example, if string is set to "[],_", only foo[1] and foo_1 will be represented internally as foo 1.

Special attention should be paid to the Verilog case. Verilog only accepts [] as legal vector indexation. Legal verilog vectors are represented internally as vectors if avtVectorize is different to no.

Illegal Verilog vectors are supported and controlled by avtVectorize as far as they are escaped and avtStructuralVerilogVectors is set to yes. For example, \foo<1> is represented internally as a vector if avtStructuralVerilogVectors is set to yes and avtVectorize is set to <>.

4. 5. Transistor Characterization

avtElpCapaLevel

Allows the user to compute differents kind of input capacitance.

0 Input capacitance is the average between up and down capacitance
1 Default, nominal up and nominal down capa are used to compute timing
2 Same behavior as if set to 1 but also minimal and maximal capacitances are computed for both transitions (6 capacitances at all).

avtTechnoModelSeparator

<char> Character that will be used as a separator between the model name and the model index. Default value is .

avtElpDriveFile

yes A ELP file specified by avtElpGenTechnoName will be printed after transistor electrical characterization.
no default

avtElpGenTechnoName

<string> Name of the generated ELP file. Default is techno.elp.

4. 6. Input Netlist and Parasitics

avtInputFilter

<string> Shell command line used to decompress an input netlist

avtOutputFilter

<string> Shell command used to compress an output file

avtFilterSuffix

<string> Suffix of the compressed files

avtDisableCompression

<string> Space separated filename list for which compression must be ignored. EXAMPLE: "*.rcx *.rep"

avtAnnotationKeepCards

transistor M character is kept before the transistor name
diode D character is kept before the diode name
resistance R character is kept before the resistance name
instance X character is kept before the instance name
capacitance C character is kept before the capacitor name
none No character is kept
all M, R, X, C, D characters are kept

avtMaxCacheFile

<int> If cache mechanisms are used, sets the maximum number of files that can be opened at the same time. Larger the value is, faster is the disk access. Default value is 128. Maximum value depend on your system (see UNIX command limit).

avtParasiticCacheSize

<int>[Kb|Mb|Gb] Size (bytes) of the memory cache for all applications dealing with parasitics. Value represents the maximum amount of information stored in memory. Increase this value to lessen disk access and speed-up application. avtParasiticCacheSize cannot be used together with compressed files.
10Mb Default
0 Disable cache and load all the parasitic information

avtFlattenForParasitic

yes HITAS flattens a hierarchical netlist in order to annotate the netlist with SPEF or DSPF parasitics. To be used together with avtCatalogueName
no default

avtVddVssThreshold

<float> Value (in volts) defining the absolute voltage value level above which a node is considered to be a power supply node. Default value is 0.5.

4. 7. SPICE Parser

avtSpiCreateTopFigure

yes Default, parser automatically creates a top-level for all elements outside of SUBCKT definition. All equipotentials are made into external connectors. The name of the top-level is the same as the filename without the extension unless a subcircuit of this name exists, in which case the name is prefixed by top_
no No top-level is created

avtSpiParseFirstLine

yes First line of all SPICE files are taken into account, unlike the behavior in standard SPICE
no First line of all SPICE files are ignored
include Default, first line of the top-level SPICE file is ignored, but the first line of included files are parsed normally

avtSpiReplaceTensionInExpressions

yes Avoids expression evaluation errors due to unhandled dynamic tensions in expression. The voltage is considered to be 0.
no Default.

avtEnableMultipleConnectorsOnNet

yes By default, there can only be one external connector per net after a netlist parse. If multiple connectors are found, they are merged into one. This can have a big drawback. Connectors required on the interface of a top level netlist can be missing. There can also be issues for ignoring instances with transparencies using hierarchical names as transparences are analysed to build nets prior to check ignored instance resistors. Setting this variable to yes allows multiple external connectors on nets so transparences are analysed during the resistor removal step without the nets being shorted already. This has an effect on ignored instances containing transparences. It affects HITAS behaviour and may make it not work in hierarchical mode.
no Default.

avtSpiMergeConnector

yes Default, connectors with the same radical, but different node indexes, will be merged (they are supposed to belong to the equipotential outside the subcircuit). The separator between the radical and the index is given by avtSpiConnectorSeparator.
no Connectors are not merged

avtSpiConnectorSeparator

<char> Character used to separate a connector radical name from its node index (ck.1, ck.2 ... for example).

avtSpiKeepNames

transistor Transistor name is kept in the database
diode Diode name is kept in the database
resistance Resistance name is kept in the database
allnodes All node names are kept for signals in the database
none No name is kept in the database
all All names are kept in the database

avtSpiKeepCards

transistor M character is kept before the transistor name
diode D character is kept before the diode name
resistance R character is kept before the resistance name
instance X character is kept before the instance name
capacitance C character is kept before the capacitor name
none No character is kept
all M, R, X, C, D characters are kept

avtSpiNameNodes

yes Default, nodes names are used rather than the node numbers
no Only node numbers are used

avtSpiNodeSeparator

<char> Character that will be used as a separator between the node name and the node number. The default value is _

avtSpiInstanceMultiNode

yes Default, allows two or more identical nodes to be declared in a subckt interface
no Only the first node declared is taken into account

avtSpiIgnoreDiode

yes Diodes are ignored by the SPICE parser.
no Diodes are characterized.

avtSpiMergeDiodes

yes Diodes are merged with neighboring transistors if the transistor is of the same type and area of the connected source or drain is 0.
no Diodes are characterized independantly.

avtSpiIgnoreVoltage

yes Voltage sources are ignored by the SPICE parser.
no Voltage sources are not ignored.

avtSpiIgnoreModel

yes Model directives are ignored by the SPICE parser.
no Model directives are not ignored.

avtSpiIgnoreCrypt

yes Encryption directives (used to indicate encrypted data) are ignored.
no The default. Encryption directives must surround encrypted test obtained by avt_EncryptSpice function.

avtSpiJFETisResistance

yes JFETs are considered to be resistances. Values are resolved by the SPICE parser.
no

avtSpiShortCircuitZeroVolts

yes Voltage sources with a value of 0 are modeled by the SPICE parser as resistances of 0 Ohms.
no

avtSpiMaxResistance

<float> If a resistance's value is greater than float (in Ohms), then the resistance is considered to be open circuit.

avtSpiMinResistance

<float> If a resistance's value is less than float (in Ohms), then the resistance is considered to be short circuit.

avtSpiMinCapa

<float> If a capacitance's value is less than float (in Ohms), then the capacitance is ignored

avtSpiOneNodeNoRc

no Removes on all nets containing only one node all parasitics information at the end of the parse.
yes

avtSpiOrderPinPower

yes Uses the name (in the same manner as avtSpiDspfBuildPower) of the instance nodes to ensure a correct order for power supply connectors.
no

avtSpiFlags
This configuration is used to control the behavior of the spice parser/driver. The values (flags) are added separated with commas.

DriveInstanceParameters Enables the drive of the instances with all their parameters
IgnoreGlobalParameters Works with DriveInstanceParameters and removes all the global parameters from the instance parameters to drive. Useful when the netlist has been flattened and the parameters inherited by the leaf instances.
KeepBBOXContent Will keep the content of the figures set as blackboxes whereas by default only the interfaces are kept.
TransfertTopLevelVcards Will transfert voltage sources connected to instances, who are defined out of a subckt in the spice file, in their corresponding circuit subckt so the Vcards can be taken into account when working on one of this instance circuit. This option is enabled by default. It can be unset by adding '!' in front of the option: '!TransfertTopLevelVcards'.
ExplicitInstanceNames If enabled then instance names specified in the netlist are prefixed by the subckt name in order to create the internally used name.

avtSpiTolerance

This variable tunes the tolerance of the SPICE parser regarding unrecognized syntaxes for R (resistances) and C (capacitances) devices.

low Parser exits when encountering unknown syntax
medium Parser continues and tries to keep only the nominal value of the device, issuing a warning message
high Same as in the medium configuration, but no warning message is issued

avtSpiHandleGlobalNodes

yes Default, global nodes defined in spice netlist without resistances will be considered equipotential.
no

4. 8. SPICE Driver

avtSpiVector

_ Default, vectors are of the shape foo_1 in output spice files
[] Vectors are of the shape foo[1] in output spice files
() Vectors are of the shape foo(1) in output spice files
<> Vectors are of the shape foo<1> in output spice files

avtSpiDriveDefaultUnits

<string> Its behavior is to indicate the parameter units to be used when instantiating a transistor. For instance, avtSpiDriveDefaultUnits = W:1e-6;L:1 will set the spice driver to drive parameter W value in micron and parameter L in meter.

avtSpiUseUnits

yes Allows the use of units in driven spice files. This is the default.
no

avtSpiDriveParasitics

yes A SPEF file will be generated while parsing a SPICE file. The loaded file will be stripped of all resistors and capacitors. The SPEF file can be used as a parasitic cache file.
no

avtSpiDriveTrsInstanceParams

no Specifics instances parameters for the models of transistors will not be driven.
yes

avtSpiDriveCapaMini

<float> When driving a Spice netlist, doesn't drive capacitances below float (in Pico-farads). Default is 10-6 pF.

avtSpiDriveResiMini

<float> When driving a Spice netlist, fix minimum value for resistances to float (in Ohms). Default is 10e-3 Ohms.

avtSpiRCMemoryLimit

<int> Amount of memory in MB allowed to creating a .SPEF file from a spice file. This option influences avtSpiDriveParasitics speed. The default value is 100.

avtSpiFlags
This configuration is used to control the behavior of the spice parser/driver. The values (flags) are added separated with commas.

DriveInstanceParameters Enables the drive of the instances with all their parameters
IgnoreGlobalParameters Works with DriveInstanceParameters and removes all the global parameters from the instance parameters to drive. Useful when the netlist has been flattened and the parameters inherited by the leaf instances.
KeepBBOXContent Will keep the content of the figures set as blackboxes whereas by default only the interfaces are kept.
TransfertTopLevelVcards Will transfert voltage sources connected to instances, who are defined out of a subckt in the spice file, in their corresponding circuit subckt so the Vcards can be taken into account when working on one of this instance circuit. This option is enabled by default. It can be unset by adding '!' in front of the option: '!TransfertTopLevelVcards'.

4. 9. VHDL Parser/Driver

avtVhdlMaxError

<int> Maximum number of errors before the VHDL structural parser abandons.

avtStructuralVhdlConfigure

yes VHDL structural driver generates the appropriate configuration statement to allow simulation.
no Default

avtStructuralVhdlSuffix

<string> Suffix of VHDL structural (netlist) file. The default is vhd

avtBehavioralVhdlSuffix

<string> Suffix of VHDL behavioral file. The default is vhd

4. 10. VERILOG Parser/Driver

avtVerilogKeepNames

yes When generating Verilog output, any internal names which are not legal verilog names are preceded by a double backslash.
no Default. Illegal names are modified to create a legal name.

avtStructuralVerilogVectors
Affects the parsing of illegal Verilog vector-signals in a netlist, i.e. vector-signals that are not indexed using the [] characters. Illegal Verilog vector-signals are supported as long as they are preceded by \, otherwise the Verilog parser issues a syntax error. Legal Verilog vector-signals are controlled by avtVectorize.

yes Force illegal Verilog vector-signals to be represented as vectors in the internal database, with regard to the value of avtVectorize. For example, \foo<1> is represented internally as foo 1 if avtVectorize is set to <1>
no Default, illegal Verilog vector-signals are represented in the internal database as they appear in the file. For exemple, \foo<1> is represented internally as foo<1>

avtStructuralVerilogSuffix

<string> Suffix of Verilog structural (netlist) file. The default is v

avtBehavioralVerilogSuffix

<string> Suffix of Verilog behavioral file. The default is v

avtVerilogMaxError

<int> Maximum number of errors before the Verilog parser abandons.

4. 11. DSPF/SPEF Parser

avtAnnotationPreserveExistingParasitics

yes Existing parasitics on nets annotated in a DSPF/SPEF file won't be overridden by the parasitics in the DSPF/SPEF file. The DSPF/SPEF information will rather be added to the existing ones.
no Default

avtAnnotationDeviceConnectorSetting

<string> Overrides the internal tool known device connector names used in DSPF/SPEF annotation. The string must contain 10 items in the following order: transistor source name, transistor gate name, transistor drain name, transistor bulk name, resistor positive connector, resistor negative connector, capacitor positive connector, capacitor negative connector, diode positive connector, diode negative connector. By default, the tool knows of "s g d b 1 2 1 2 1 2" and "s g d b pos neg 1 2 1 2".

Example:

avt_config avtAnnotationDeviceConnectorSetting "src gate drn blk 1 2 1 2 1 2"

avtSpiDspfBuildPower

yes Only used for DSPF annotation. When creating a figure from DSPF information, use the avtGlobalVddName, avtGlobalVssName, avtVddName and avtVssName to detect power connections on the instance, so they are created on the boundary of it instead of being merged with all unknown connectors.
no

avtSpiDspfLinkExternal

yes Only used for DSPF annotation. When an external connector is not connected to anything, and if there is an internal signal with the same name, then the connector is assumed to be on this signal.
no

avtSpiPinDspfOrder

yes Only used for DSPF annotation. Order of connector of an instance is the one described in the DSPF instead of the one described for the instance interface.
no

4. 12. General Configuration

tasHierarchicalMode

yes Hierarchical analysis mode.
no Default, flat transistor analysis mode.

tasBlackboxRequiresTimings

yes HITAS Reads a hierarchical netlist where some instances are considered as blackboxes. The name of these instances should be specified using the avt_SetBlackBoxes command. The hierarchical netlist is then flattened to the transistor level, apart from the blackbox instances, to generate a hybrid transistor and instance netlist. The database construction is performed on this hybrid netlist and then HITAS will incorporate timing for the blackboxed instances from an external timing database for the model of the instances which must exist.
no Default

tasTreatBlackboxHierarchically

yes HITAS Reads a hierarchical netlist where some instances are considered as blackboxes. The name of these instances should be specified using the avt_SetBlackBoxes command. HITAS creates an intermediate subcircuit containing only the non-blackbox instances. A top-level is also created, and instantiates the intermediate subcircuit and the blackbox instances. Database construction is performed on the intermediate subcircuit.
no Default

tasFigName

<string> Name of the subcircuit to read, or to rename the database.

tasBefig

yes Generates a behavioral description of the design
no Default

tasFlatcells

yes Flattens the timing views of all the models given in the catalogue file specified by avtCatalogueName.
no Default

tasSilentMode

yes HITAS redirects stdout and stderr respectively to .tou and .ter files.
no

tasPathFactorisation

yes HITAS keeps paths starting and stopping at factorization points that are not reference points. This in order to decrease the number of path of the TTX.
no Default

4. 13. Disassembly

4. 13. 1. Functional Analysis

yagAnalysisDepth

<int> Allows the user to set the depth for the functional analysis. This is the number of gates that will be taken into account for the functional analysis, so that HITAS can detect re-convergence in the circuit. Default is 7.
0 Functional analysis process is disabled

yagHzAnalysis

yes Allows functional analysis through high impedance nodes.

yagMaxBranchLinks

<int> Maximum number of links in a cone branch.

yagRelaxationMaxBranchLinks

<int> Used to limit the maximum number of links for the difficult gates for which functional dependencies could not be resolved.

yagBddCeiling

<int> Limits the maximum number of BDD nodes which are allowed to be created for the resolution of any Boolean expression. If this limit is exceeded the operation is abandoned. Default is 10 000.

yagElectricalThreshold

<float> Used in electrical resolution of conflicts to determine the zones corresponding to the high, low and conflictual states. Default is 4, implying that the high and low states are represented by zones 1/4 of the zone Vss-Vdd.

yagUseStmSolver

yes Precise current calculations using technology files are used in electrical conflict resolution.
no Default, basic transistor dimensions are used in electrical conflict resolution.

yagRelaxationAnalysis
During the gate construction phase, HITAS attempts to resolve all functional dependencies before building a particular gate. However, in particular cases of looped dependencies, this may not be possible for all gates.

yes Functional dependencies are ignored to resolve these gates.
no Default, HITAS tries to use as much information as possible.

yagDetectGlitchers

yes A branch containing two transistor with mutually exclusive gate drivers and which cannot be part of another gate are assumed to exist dynamically. They are therefore not removed by the functional analysis. This is the default.
no

yagKeepRedundantBranches
For any CMOS dual cones extracted, if supplementary branches are added at a later stage of the disassembly and the gate remains non-conflictual, then these branches are considered to be functionally redundant.

yes The branches are kept.
no Default, the branches are removed.

yagPullupRatio

<float> Used in the detection of pull-up or pull-down resistance transistors. Default is 10, implying that a transistor is a pull-up if an estimation of its resistance is greater than 10 times the resistance of the most resistive current path to ground. Similarly for pull-pown resistances.

4. 13. 2. Transistor Orientation

yagSimpleOrientation

yes Activates a simple transistor orientation heuristic. Can sometimes accelerate the disassembly, however, it is more robust to rely exclusively upon the functional analysis.
no Default.

yagUseNameOrientation

yes Exploits the _s naming convention for transistor orientation.
no Default.

yagBlockBidirectional

yes Bidirectional transistors are not allowed.
no Default.

yagCapacitanceCones

yes Default. Build cones on nodes with only capacitances. Necessary to calculate the out of path capacitance.
no Disables construction of cones on only capacitance nodes.

yagTestTransistorDiodes

yes Default. Any transistor with the gate shorted to a source or a drain is considered as a diode.
no Disables diode detection.

yagMutexHelp

yes A file with extension '.mutex' is generated containing help for MUTEX settings on external pins or memory nodes necessary to correctly orient the transistors.
no Default.

4. 13. 3. Latch Recognition

yagSimpleLatchDetection
A simple structure based recognition algorithm which handles the various cases of double inverter loops. This approach is not usually required and is not guaranteed to be formally correct but can sometimes help in cases where the automatic approach is too CPU intensive. The following values can be given for this variable:

memsym Double inverter loops are also analyzed to see if they correspond to a simple symmetric bitcell. In this case the the command of the bitcell is the input of the pass transister or transfer gate connected directly to the loop.
levelhold Double inverter loops are considered to be level-hold or buskeeper structures (i.e. not latches).
strictlevelhold Double inverter loops are considered to be level-hold or buskeeper structures (i.e. not latches), but only if only one side of the inverter loop is connected.
latch Double invertor loops are treated as latches without any anlysis, unless a level-hold or memsym option is also activated and these forms match. Commands are guessed without analysis. This option helps if double inverter loops are used to latch the output of complex multiplexors.

The above options can be concatenated by separating the individual options with a '+' character. However the combinations "levelhold+strictlevelhold" and "levelhold+latch" make no sense. The search options are applied in the order specified above. By default all the options are disabled.
yagAutomaticLatchDetection

yes Advanced latch detection algorithm based on Boolean loop analysis is activated. Default.
no Advanced latch detection is disabled.

yagSetResetDetection

yes Only works with yagAutomaticLatchDetection set to yes. Asynchronous latch commands are marked asynchronous instead of being marked commands. False timing arcs (corresponding to the conditioning of data by an asyn or the conditioning of an async by a clock) are disabled.
remove Does the same as the yes mode. In addition marks as non-functional any branches corresponding to an asynchronous write.
no Default.

yagAutomaticRSDetection

mark Default. Only works with yagAutomaticLatchDetection set to yes. Supplementary RS bistable detection algorithm is applied to automatically detected latches. Only NAND/NOR types are accepted. Any detected RS bistable loops will be marked and reported but not treated as latches.
no Automatic RS detection is disabled. Recognition depends upon yagAutomaticLatchDetection
mark+latch One of the gates of the loop is considered a latch. The latch is the gate with the largest number of outputs.
mark+legal The algorithm assumes that an RS structure always remains in its legal states. Timing arcs are suppressed accordingly. For NOR-based RS, the following timing arcs are suppressed: S(f) to QB(r), R(f) to Q(r), QB(r) to Q(f) and Q(r) to QB(f). For NAND-based RS, the following timing arcs are suppressed: S(r) to QB(f), R(r) to Q(f), QB(f) to Q(r) and Q(f) to QB(r).
mark+illegal The algorithm assumes that an RS structure may enter an illegal state. Less timing arcs are suppressed than when the tool assumes that an RS structure always remains in its legal states. For NOR-based RS, the following timing arcs are suppressed: Q(r) to QB(f) and QB(r) to Q(f). For NAND-based RS, the following timing arcs are suppressed: Q(f) to QB(r) and QB(f) to Q(r).

yagAutomaticMemsymDetection

yes Only works with yagAutomaticLatchDetection set to yes. Supplementary symmetric memory detection algorithm is applied to automatically detected latches. Symmetric memories are memorizing elements such as bitcells for which data is written in both or either side of the memorizing loop. Both sides of the loop are marked as latches is order to verify all cases.
no Default.

yagDetectDynamicLatch

yes Internal tri-state nodes are considered to be dynamic latches for functional modeling and timing analysis purposes. A special algorithm, similar to that used in the automatic latch detection, is used to identify the latch commands and generate an accurate latch model.
no Default.

yagDetectPrecharge

yes An algorithm designed to detect automatically most kinds of precharge nodes is activated. The algorithm is particularly designed for domino precharge style designs.
no Default.

yagBleederStrictness

A level between 0 and 2 defining the strictness of the bleeder detection algorithm. The value determines the kind of gate which can be tolerated in the bleeder loop.

0 any CMOS gate is acceptable
1 default, any CMOS dual gate is acceptable
2 it must be an inverter

yagStandardLatchDetection
Deprecated. This structure based latch recognition technique is activated by default as a catch-all. It will probably be removed in a future version.

yes Default, standard latch detection algorithm is activated.
no Standard latch detection algorithm is disabled.

yagLatchesRequireClocks

yes Any latch which does not have a command which is at the end of a path from a specified clock is not considered to be a latch. If this option is used, then extreme care should be taken to specify the clocks to avoid problems in any subsequent analysis.
no Default.

yagDetectClockGating

yes If clocks are configured before the disassembly phase then reconvergence between clock and data will be detected, appropriate timing check and data filtering directives are automatically generated.
check Same as above except only the timing checks are added.
filter Same as above except only the data filtering directives are added.
no Default.

yagDetectDelayedRS

yes Detect special type of NAND/NOR bistable loop structure containing additional inverters to add delay in the loop. Results in the same handling as the legal setting for RS detection. This type of structure is commonly used to generate non-overlapping clocks.
no Default.

4. 13. 4. Pattern Matching

yagUseGenius

yes Extends the simple pattern recognition of FCL to allow the recognition of hierarchically defined structures of generic size.
no Default

yagUseOnlyGenius

yes Same as yagUseGenius but HITAS stops the execution after the hierarchical pattern recognition phase.
no Default

4. 13. 5. Cone Output Files

avtVerboseConeFile

yes Generating a .cnv cone file result in a more readable version but which is not suited for GUI vizualisation.
no Default.

avtNormalConeFile

yes A normal .cns cone file is produced.
no Default.

avtFullConeFile

yes .cnv or .cns cone files are generated with parasitic information.
no Default.

yagGenSignature

yes Signatures are generated for each cone which are used to associate icons with the cones.
no Default.

4. 14. Timing DB Construction

4. 14. 1. Special Elements

tasTreatPrecharge

yes Precharged signals are also considered as precharged if its name is suffixed by _p or if it is declared in the INF file. To be used only in the flat analysis mode.
no Default

tasMemoryCharacterization

yes Default, HITAS adds the latches' intrinsic setup, hold and access delays
no

tasPreserveConnectorsDirection

yes Preserve connectors direction if there are level constraints on connectors.
no

4. 14. 2. Output Files

tasGenerateConeFile

yes HITAS generates the .cns or .cnv files containing the cone view. To be used only in flat analysis mode.
no Default

4. 14. 3. Delay Models

stmCacheSize

<int>[K|M] Size of the memory cache for all applications reading the STM file. The default unit is the Octet. If the value is followed by either K or M the unit is the kilo-Octet or the Mega-Octet.
0 Default, the cache utilization is disabled and all the timing model information are loaded. stmCacheSize cannot be used together with compressed files.

stmShareModel

yes Identical cones will share the same timing model. There is a 1% tolerance in the matching of identical cones, regarding capacitance related parameters of the model. Extractors, especially when used in crosstalk mode, may show slight variations in the values of extracted capacitances for different instances of a same cell.
no Default

tasShortNamesForModels

yes HITAS will use model numbers instead of the model names
no Default

4. 14. 4. Delays

avtNewSwitchModel

yes HITAS will use an enhanced switch delay calculation model which accurately takes into account contributions from both transistor of the switch and also handles the difference between the opening times of the two transistors.
no Default

tasDelayPropagation

yes Default, HITAS will propagate through a gate the slope of this gate's input having the latest arrival time.
no HITAS will propagate through a gate the largest (or smallest) slope. Adds additional pessimism.

tasRefineDelays

yes HITAS will will perform an additional delay calculation phase after DTX generation using the slope propagation algorithm specified in tasDelayPropagation. This allows perfect delay value correlation with the result of delay recalculation after a slope or lod change.
no Default.

tasSwitchCapacitanceFactor

<int> Percentage of the 'out-of-path' capacitances associated with an input connector taken into account during a flat analysis. Default is 100. Affects only TTX and DTX file generation and does not change the delay computation.

tasPathCapacitanceFactor

<int> Percentage of the out-of-path capacitances taken into account. Default is 100.

tasPathCapacitanceDepth

<int> To be used together with tasPathCapacitanceFactor. Controls across how many transistor the out-of-path capacitance should be counted. Default is 1.

tasStrictPathCapacitance
To be used together with tasPathCapacitanceFactor.

yes Any out-of-path capacitance on internal nodes of any gate is ignored.
no Any out-of-path capacitance on internal nodes of a gate is considered on the gate output.
latch Default. Any out-of-path capacitance on internal nodes of a latch is ignored.

tasMaxPathCapacitanceFanout

<int> To be used together with tasPathCapacitanceFactor. If the number of gates contributing to an out-of-path capacitance for a given cone exceeds this value then only the largest contribution is taken into account. Effectively a mutual exclusion is assumed. Default is 15.

4. 14. 5. RC Networks

tasCalcRCDelays

no Only the capacitances will be taken into account to compute the propagation delays
yes Default

tasMergeRCAndGateDelays

yes Merges the gate and RC delays in the flat analysis mode
no Default

rcxMinRCSignal

<int> If the sum of resistances multiplied by the sum of capacitances on an RC network is less than int (ps), then the RC network is ignored. Default is 1 ps.

rcxCapaLoadMaxRC

<int> If the sum of resistances multiplied by the sum of capacitances on an RC network is less than int (ps), then the load of the driving gate is modeled by an equivalent substrate capacitance. Default is 5 ps.

rcxMaxDeltaLoad

<int> If the rcxCapaLoadMaxRc test fails and the difference between an equivalent substrate capacitance model and a PI network model is less than int (ps), then the equivalent capacitance model is used, otherwise the PI model is used. Default is 1 ps.

tasRCDriverCalcMode
Controls the choice of which node or nodes of an RC network are driven by a preceding gate.

all All possible input nodes of the RC are considered driven.
all_direction All nodes of the RC which can be driven by the actual transition are assumed driven.
select_direction One node of the RC which can be driven by the actual transition is assumed driven.
all_gates The first three options apply to RC networks driven by any type of gate.
parallel_gates The first three options apply to RC networks driven by gates containing parallel transistors or current paths.
none One node of the RC is considered driven.
auto Automatic mode which differentiates input transition and chooses one or all drivers based on gate type.

One of the first three options can be concatenated with one of the next two by separating the individual options with a '+' character. The default setting is "all_direction+parallel_gates".
rcxAweMatrix

always Matrices are always used to compute the moments for RC delay with AWE algorithm
ifneed Default, matrix is not used if RC network has one node driver and has a tree topology. In this case, a faster algorithm is used to compute the moments.
never No matrix is used. RC networks which can't be handle by the faster algorithm are not computed.

rcxDelayCacheSize

<int>[Kb|Mb|Gb] Cache size for gate output equivalent load and RC moment in AWE delay evaluation. When one of these values is computed, results are stored in the delay cache. If later re-computation is needed, results can be retreived immediatly. This cache is mainly used within the timing abstration engine. Default unit is the byte.
0 Disables the cache. Default value is 10Mb.

4. 15. Path Browsing

avtPrecisionLevel

0 Default, slope propagation is done according to tasDelayPropagation
1 When computing propagation time for a path, the tool re-propagates the slope from start point, and computes delays along the path accordingly.

avtMaxPathPeriodDepth

<int> When performing a path search, the tool needs a parameter to avoid loop search. This is the maximum number of period that a path can go through or the maximum number of latches at the same clock edge. Default value is 1.

avtTransparentPrecharge

yes Sets avtMaxPathPeriodDepth=1 only for the precharges so it's possible to report paths through domino precharges.
no Default.
unfiltered Same as yes but deactivates the precharge filtering effect so non existing path due to filtering will be kept.

4. 16. SDC Support

sdcUnits
Sets the time unit and capacitance unit used in the Synopsys Design Constraint (SDC) files. Unit for time and unit for capacitance should appear both in a space-separated list (ex: "1ps 1ff"). Available values are:

1ps Default
10ps
100ps
1ns
1ff
10ff
100ff
1pf Default

4. 17. Static Timing Analysis

stbDetailedAnalysis

yes Enables multi-switching-windows analysis with the STA engine. The STA engine will use more memory and cpu.
no Default

stbDetailedGraph

yes The STA engine uses the .dtx file and computes switching windows for each point of the timing graph. It is required for crosstalk analysis.
no Default

stbTraceMode

yes The STA engine displays all intermediary values of the switching windows calculations on th standard output. Useful to see how the relaxation progresses.
no Default

stbReportFile

yes Default, the STA engine generates a .str timing report file containing details of all setup and hold slacks for reference points.
no the STA engine does not generate the .str timing report file

stbOutFile

yes The STA engine generates a .sto switching windows file containing details of the switching windows of reference points.
no the STA engine does not generate the .sto switching windows file

stbSetupOnly

yes Only errors due to setup time violations are reported.
no Default

stbHoldOnly

yes Only errors due to hold time violations are reported.
no Default

stbEnableCommandCheck

yes Commands will be checked for violations.
no Default

stbMonoPhase

flip_flop a latch clocked on the same phase than the latch generating its input data is assumed to be a flip-flop.
transparent a latch clocked on the same phase than the latch generating its input data is always transparent.
errors a latch clocked on the same phase than the latch generating is input data is not allowed, and an error is reported.

stbSaveErrors

yes Errors are redirected to a separate .ste error file.
no Default

stbSilentMode

yes The STA engine displays neither errors nor warning on the standard output.
no Default

stbTopLevelPath

yes Violations are computed using only the paths at the top level (i.e. the interconnections at the top level).
no Default

stbWorstCaseAnalysis

yes Worst case analysis is performed by assuming that in the initial conditions, there is no latch transparency.
no Default

stbCorrelatedSkewAnalysisDepth

number Specifies the maximum search depth allowed to find common clock path when computing setup and hold values at each node. The value 'full' means unlimited.
full Default

stbStabilityCorrection

yes The false paths and false slacks are taken into account to correct the global stability time computed by STB. This corrects false data lags hence too pessimistic setup and hold computations.
no Default

StbSuppressLag

latch Transparency (data lag) will be ignored for latches.
precharge Transparency (data lag) will be ignored for precharges.
yes Transparency will be ignored for any of the above.

stbHelpForSetup

yes Gives additional information to help setting the stability configuration. The information is driven in the log file.
no Default

4. 18. Statistical Analysis

spiActivateStatisticalFunctions

yes Enables montecarlo runs. The statitical functions will no more return the nominal values.
no Default

avtStatisticalDiscretisation

number Apply a discretisation to the values returned by random functions. The default value is 10. A high value means less discretisation but 0 deactivates the discretisation. This variable can have a great impact on HiTas speed.

4. 19. Crosstalk Analysis

4. 19. 1. Running

stbCtkWorstBeginCondition

yes The SI engine performs a worst case static timing analysis with crosstalk. All aggression is assumed initially. Any false aggression is detected and removed.
no Default

stbCrosstalkMode

yes Enables crosstalk analysis.
no Default

stbCtkObservableMode

yes Default. The SI engine performs a best case static timing analysis with crosstalk. No aggression is assumed initially. Any aggression is detected and added. Uses a less pessimistic algorithm to detect observable aggression.
no

stbCtkNoInfoActif

yes The SI engine considers aggressors not defined in the timing view as active aggressors. No information on an aggressor are usually due to a coupling capacitance between usual net and an internal gate net.
no Default.

stbCtkMinOccurenceProbability

value [IN ALPHA DEVELOPMENT STAGE] Defines the probability value (from 0 to 1) under which a agression occurence probability is considered as not interesting during a crosstalk analysis. Default value is 1.
no Default.

stbCtkReportFile

yes The SI engine generates a .ctk crosstalk report file.
no Default.

4. 19. 2. Models

stbCtkMargin

<float> Minimum delay between two switching windows implying that there is no possibility of aggression. Default value is 0 picoseconds.

ctkNoiseDefaultResi

<float> Resistance in Ohms representing the driving strengh of input pins, in order to obtain pertinent peak noise values.
10000 Default value

rcxCtkModel
Model used to compute elementary delay when taking into account crosstalk effect if an aggression is detected.

MILLER_0C2C Coupling capacitance is removed or replaced to a ground capacitance with a doubled value.
MILLER_NOMINAL Default, coupling capacitance is replaced to a ground capacitance with a value multiplied by 0.0 to 2.0 according to relative slope computed without coupling effect between victim and its aggressor.

rcxMinRelCtkFilter

<float> Number between 0 and 1. If the ratio between one coupling capacitance and the total capacitance is less than float, then the filtering of this coupling capacitance is controlled by stbCtkNoInfoActif. Default is 0.05

rcxMinRelCtkSignal

<float> Number between 0 and 1. If the ratio between the sum of coupling capacitance and the total capacitance is less than float then all the coupling capacitances are filtered. Default is 0.05

rcxCtkSlopeDelay

SLOPE_DELAY_CTK Default, basic slope is used during delay calculation. Gives pessimistic results, but is faster
SLOPE_DELAY_ENHANCED Removes the contribution of the victim on the slopes of its aggressors. More precise but requires more computation time

rcxCtkSlopeNoise

SLOPE_CTK Default, uses worst slopes with crosstalk to compute voltage noise
SLOPE_NOMINAL Uses slopes computed without aggression to compute voltage noise
SLOPE_REAL Removes the contribution of the victim on the slopes of its aggressors. Requires more computation time but gives better results

4. 19. 3. Convergence

stbCtkMaxIteration

<int> Defines the maximum number of iteration the SI can perform. Default value: 999

stbCtkminSlopeChange

<int> When no further aggression is detected or removed, this variable represents the minimum slope variation, in ps, that induces slope re-calculation. Default is 2

stbCtkMaxLastIter

<int> When no further aggression is detected or removed, this variable represents the maximum number of iterations of slope re-calculation. Default is 3

4. 19. 4. Reports

ctkDeltaDelayMin

<int> Minimum amount, in ps, of the propagation delay variation, versus crosstalk-free propagation delay. If the variation is greater than int, then it is reported in the .ctk file. Default is 0 ps.

ctkDeltaSlopeMin

<int> Minimum amount, in ps, of the slope variation, versus crosstalk-free slope. If the variation is greater than int, then it is reported in the .ctk file. Default is 0 ps.

ctkNoiseMin

<int> Minimum value, in mV, of the voltage noise to be reported in the .ctk file.

ctkCapaMin

<int> Number between 0 and 100. Minimum percentage of coupling capacitance. If the ratio of the coupling capacitance on a net is greater than int then it is reported in the .ctk file.

stbCtkMaxReportedSignals

<number> Number of signals to report at each crosstalk iteration. Setting the number to 0 disables the report generated at each iteration. Default is 0.

4. 19. 5. Scores

stbCtkCoefNoise

<int> Between 0 and 10. Specifies the noise voltage score part of the total score. Default is 4.

stbCtkMinNoise

<int> Minimum noise voltage score under which no report for this net is provided.

stbCtkCoefInterval

<int> Between 0 and 10. Specifies the interval score part of the total score. Default is 3.

stbCtkMinInterval

<int> Minimum interval score under which no report for this net is provided.

stbCtkCoefCtk

<int> Between 0 and 10. Specifies the crosstalk score part of the total score. Default is 2.

stbCtkMinCtk

<int> Minimum crosstalk score under which no report for this net is provided.

stbCtkCoefActivity

<int> Between 0 and 10. Specifies the activity score part of the total score. Default is 1.

stbCtkMinActivity

<int> Minimum activity score under which no report for this net is provided.

4. 20. Timing Abstraction

4. 20. 1. Input Files

tmaLibraryFile

<string> Allows the user to specify an input library file containing the areas of the cells

tmaLibraryName

<string> Allows the user to specify the name which will appear in the library() staement

4. 20. 2. Output Files

tmaFunctionalityMode

w The timing abstraction engine generates a behavioral description
r The timing abstraction engine reads a behavioral description
t Default, the timing abstraction engine generates timing information only

tmaLibBusDelimiter

[] Default, vectors in the lib file are of the kind foo[1]
_ Vectors in the lib file are of the kind foo_1
- Vectors in the lib file are of the kind foo-1
{} Vectors in the lib file are of the kind foo{1}
() Vectors in the lib file are of the kind foo(1)
<> Vectors are in the lib file are of the kind foo<1>

tmaDriveCapaout

yes Timing abstraction engine prints the output connectors capacitance in the .lib file
no Default

tmaLibSlewDerate

<float> Affects the slew_derate_from_library attribute of the Liberty file. Value should be comprised between 0 and 1.

tmaLibDriveTableIndex

yes Enables indexes in LIB timing groups.
no Default

avtPowerCalculation

yes Enables leakage and switching power calculation.
leakage Enables leakage power calculation.
switching Enables switching power calculation.
no Default

4. 20. 3. Units

tmaCapacitanceUnit

pf Capacitance unit in pico-Farads
ff Default, capacitance unit in femto-Farads

tmaTimeUnit

ns Time unit in nanoseconds
ps Default, time unit in picoseconds

tmaLeakagePowerUnit

<string> Leakage power unit in LIB file. Valid values are 1mW, 100uW, 10uW, 1uW, 100nW, 10nW, 1nW, 100pW, 10pW and 1pW.
1uW Default, leakage power unit.

4. 21. Pattern Matching

fclLibraryName

<string> Name of the file containing the list of cells in the user-defined cell library used. The default is LIBRARY.

fclLibraryDir

<string> Access path to the directory containing the user-defined cell library used. Default is a directory /cells in avtWorkDir.

fclGenericNMOS

<string> A colon separated list of transistor model names which the FCL pattern-matching engine considers will match to any N-type transistor. If a pattern netlist contains non-generic N-channel transistors then these transistors will only match to transistors with an identical model. Default is tn:TN.

fclGenericPMOS

<string> A colon separated list of transistor model names which the FCL pattern-matching engine considers will match to any PMOS transistor. If a pattern netlist contains non-generic P-channel transistors then these transistors will only match to transistors with an identical model. Default is tp:TP.

fclWriteReport

yes A correspondence file is created if the -fcl option is used. This file details all the recognized instances.
no Default

fclAllowSharing

yes Matched cells are allowed to share transistors.
no Default

fclCutMatchedTransistors

yes Matched transistors are eliminated from the transistor netlist. Results in a strict partitioning of the cones and the matched cells.
no Default

fclMatchSizeTolerance

<int> Percentage tolerance for matching transistor sizes.

fclTraceLevel

<int> Number greater than 0. Trace information is displayed during the pattern-matching phase.

fclDebugMode

<int> Number greater than 0. Additional debugging information is displayed during the pattern-matching phase.

4. 22. Hierarchical Pattern Matching

gnsLibraryName

<string> Name of the file (recognition library) containing the list of cells to recognize. Default is LIBRARY.

gnsLibraryDir

<string> Access path to the directory containing the recognition library. Default is directory cells/ in avtWorkDir.

gnsKeepAllCells

yes All matched structures are extracted from the netlist.
no Default

gnsTemplateDir

<string> Directory where to find the GNS templates. Default is $AVT_TOOLS_DIR/gns_templates.

gnsTraceLevel

<int> From 0 to 6. Indicates the level of trace displayed during the recognition phase. Default is 0.

gnsTraceFile

<string> Name of the output trace file. Default is stdout.

gnsTraceModel

<string> When tracing the recognition, indicates the name of the recognized model to trace. If not specified, traces all models.

gnsFlags
This configuration controls the behavior of GNS. The values (flags) are added separated with commas. Available flags are:

EnableCore Enable the generation of a core file for a crash in a user compiled API.
NoGns Disables the generation of the .gns file
VerboseGns Produces a more readable .gns file.
NoOrdering Disables the top-level instance connectors reordering. Should not be set if using the BEG functions.

4. 23. Simulator Linking

4. 23. 1. Simulation Tool Parameters

simToolModel

Spice Technology files are interpreted in the same way as Berkeley Spice.
Hspice Technology files are interpreted in the same way as Hspice. This is the default setting unless simTool is set.
Eldo Technology files are interpreted in the same way as Eldo.
Titan Technology files are interpreted in the same way as Titan.

simTool

Spice Generates spicedeck and sets simulator linking options for Berkeley Spice.
Hspice Generates spicedeck and sets simulator linking options for Hspice. This is the default setting unless simToolModel is set.
Eldo Generates spicedeck and sets simulator linking options for Eldo.
Titan Generates spicedeck and sets simulator linking options for Titan.
Titanv7 Generates spicedeck and sets simulator linking options for Titanv7.
Mspice Generates spicedeck and sets simulator linking options for Mspice.
Ltspice Generates spicedeck and sets simulator linking options for Ltspice.
Ngspice Generates spicedeck and sets simulator linking options for Ngspice.

avtSpiceString

<string> $ Command line used to call the electrical simulator. The syntax is string $, where string is the full command line for the simulator.

simSpiceOptions

<string> Simulator options written into the Spice Deck with a .OPTION statement

simTransistorAsInstance

yes Transistors are written as instances (with an 'X') in the spice file
smart Each transistors is written as instance or not depending on the its original setting
no Default

avtSpiceOutFile

$.<string> Output format generated by the simulator, containing the simulation results. Multiple formats may be concatened using the character :. string is the suffix of the output file.

avtSpiceStdoutFile

$.<string> Output format generated by the simulator, for stdout redirection string is the suffix of the output file. Default is $.out

simAllowOverwriteFile

yes Default, allows overwrite of existing files when running a simulation.
no File overwriting not allowed.

simRemoveFiles

yes Files written by HITAS for simulation are removed after execution
no Default

simTechnologyName

<string> Name of the technology file. Appears in the spice deck in a .INCLUDE statement. Multiple file names can be given using commas to separate them.

4. 23. 2. Extraction of the Simulation Results

simUsePrint

yes Default, generates a spice deck with .PRINT statements printing simulation results as curves represented as tabular data. Delay and slope values are then computed by HITAS. CPU and disk expensive.
no

simUseMeasure

yes Generates a spice deck with .MEASURE statements directly extracting delay and slope values from the simulation results.
no Default

simMeasCmd
To be used in combination with SimUseMeasure. Explicits the .MEASURE statements used in the spice deck.
    Metadata are string that will be automatically replaced with the simulation information (label, nodes names ...) For the following <n> have to be 1 for the trigger and 2 for the target (set by user).
  • %l will be the label of the extraction.
  • %s<n> will be the (trigger/target) node name.
  • %v<n> will be the initial value of the (trigger/target) node.
  • %t<n>{<rise>,<fall>} will be the (trigger/target) transition and the syntax of <rise> and <fall> for the simulator.
  • %n<n>{<last>} will be the (trigger/target) number of transition and the syntax of <last> for the simulator.
Example: .meas tran %l TRIG v(%s1) val=%v1 %t1{rise,fall}=%n1{LAST} TARG v(%s2) val=%v2 %t2{rise,fall}=%n2{LAST}.
simExtractRule
Allows the user to specify the exact stimuli with metadata to be recognized to get result from simulation result file (used when SimUseMeasure is set to yes).
    The string is composed of three separated parts, with colon as separator.
  • First part: the type of pattern recognition. Value can be line or table.
  • Second part: the mark-up of start and end for pattern recognition. Starting and ending mark-up are encapsulated by slash.
  • Third part: the exact pattern containing metadata to be recognized. In case of table recognition, each metadata is considered as followed by a return.
    Metadata are unknow string to be matched.
  • %l represent the extraction label.
  • %i represent a string to be ignored.
  • %v represent the value associated with the label.
  • %0 represent a value to be ignored.
Example: line:/EXTRACT INFORMATION/1****/:* %l = %v targ= %0 trig= %0 applied to

**************** EXTRACT INFORMATION *********************
*
* a_up_d_down_delay = 1.5e-12 targ= 5e-15 trig= 15e-8
* a_down_d_up_delay = 1.2e-12 targ= 5e-15 trig= 15e-9
*
1****
*
* a_up_d_down_slope = 1.5e-12 targ= 5e-15 trig= 15e-8

will match a_up_d_down_delay and a_down_d_up_delay.
simDriveAliasCorrespondence

yes If simSignalAlias or simTransistorAlias is also set, correspondence between original name and their alias will be printed in the spice deck
no Default

simSignalAlias

<string> Signals names in the critical path will be replaced by string followed by a number.

simTransistorAlias

<string> Transistor names in the critical path will be replaced by string followed by a number.

simAnalysisDepth

<int> Maximum depth to analyze correlated signals. Default is 1. This variable can reveal false paths.
0 No correlated signals analysis

cpeMaxVariables

<int> Maximum number of variables below which CPE will try an exhaustive search for the best path propagation solution. Default is 20.

cpePrechargedMemsym

<yes> CPE will consider the symmetric memories to be precharge when computing propagation conditions.
<no> Default.

4. 23. 3. Simulation Conditions Parameters

simOutLoad

dynamic The gate/drain/source capacitances of out-of-path transistors are modeled in the spice deck as nominal capacitances. Recomended, need the electrical parameters of the transistors to be loaded before spice deck generation
transistor Default, the gate/drain/source capacitances of out-of-path transistors are modeled in the spice deck as blocked transistors. It can increase significantly the size of the spice deck, and has very small impact on results accuracy.
none No out-of-path capacitances. Debugging purpose.

simPowerSupply

<float> Simulation voltage in Volts. Default is 5 Volts.

simTemperature

<float> Simulation temperature in Celsius degrees. Default is 70C.

simTransientTime

<float> Duration of the simulation in seconds. Default is 100e-9 seconds.

4. 23. 4. Simulation Transient Parameters

simTransientStep

<float> Calculation step, in seconds, for the simulation and the internal data representation. Default is 1e-12 seconds.

simDcStep

<float> Accuracy step, in Volts, of the static parameters evaluation when using HITAS, and step of the SPICE analysis in DC mode. Default is 1e-3 Volts.

4. 23. 5. Simulation Thresholds Parameters

simVthHigh

<float> Between 0 and 1. High threshold of the slope as a percentage of the Vdd value. Default is 0.8

simVthLow

<float> Between 0 and 1. Low threshold of the slope as a percentage of the Vdd value. Default is 0.2

4. 23. 6. Simulation Input/Output Constraints Parameters

simInputStartTime

<float> Starting time of the input slope in seconds. Default is 0.

simSlope

<float> Transient time of the slope in seconds. Default is 200e-12 seconds.

4. 24. API Specific

apiFlags
Controls the behavior of the GNS API. The values (flags) are added separated with commas. Available flags are:

ttvUseInstanceMode Sets the TTV functions to generate/use one timing view per instance of the same matched subcircuit.
ttvDriveDTX Enables the drive of the .dtx and .stm files for timing views created with the TTV functions

4. 25. SSTA Analysis

avtSSTACacheSize

<float>[unit] Size of the memory allowed to read a set of SSTA stored files. The default value is 500Mb.