2. Overview

2. 1. Static Timing Analysis

The advent of semiconductor fabrication technologies now allows high performance in complex integrated circuits.

With the increasing complexity of these circuits, static timing analysis (STA) has revealed itself as the only feasible method ensuring that expected performances are actually obtained.

In addition, signal integrity (SI) issues due to crosstalk play a crucial role in performance and reliability of these systems, and must be taken into account during the timing analysis.

However, performance achievement not only lies in fabrication technologies, but also in the way circuits are designed. Very high performance designs are obtained with semi or full-custom designs techniques.

The HITAS platform provides advanced STA and SI solutions at transistor level. It has been built-up in order to allow engineers to ensure complete timing and SI coverage on their digital custom designs, as well as IP-reuse through timing abstraction.

Furthermore, hierarchy handling through transparent timing views allows full-chip verification, with virtually no limit of capacity in design size.

2. 2. Signal Integrity Analysis

HITAS crosstalk engine is coupled with static timing analysis (STA) engine and is based upon a multi-switching windows refinement algorithm.

Crosstalk effects are then fully handled in timing checks. Precise delay update is done thanks to current source models for gate, and non-linear charge transfer models for effective wire load computation.

Detailed SI report provides:

The graphical user interface (GUI) allows easy execution of the crosstalk analysis.

2. 3. Applications

HITAS can be used on a wide range of ICs, such as Micro-Processors, Micro-Controllers, Memory Controllers, Custom IPs or Standard-Cell Libraries (Arithmetic Units, Data-Paths...). It provides the following benefits:

Timing sign-off

Signal Integrity sign-off

Design and debug

IP Reuse (.lib files generation)

2. 4. Key Features

HITAS provides the following features: