6. Behavioral Optimization

One often wants to have a compact behavioral description. In order to optimize the VHDL|Verilog, Yagle disposes of three means:

6. 1. Inverter Minimization

Inverter minimization reduces a even chain of inverters to a single buffer, and an odd chain of inverters to a single inverter. This optimization is compatible with timing back-annotation of first level: the delay of the reduced buffer or inverter is the sum of the delays of the chain of inverters.

If timing back-annotation is of level two or three, inverters are split into up and down expressions, and are not minimized.

6. 2. Expression Simplification

When expression simplification is invoked, Yagle analyze each cone, and identifies the NOR, NAND and XOR expressions. This optimization is compatible with timing back-annotation of first level. The delay associated with the cone does not change.

If timing back-annotation is of level two or three, no simplification is done.

6. 3. Signal Suppression

Signal suppression can lead to aggressive optimization, as we will see in the following example. The principle is to replace a signal S by its expression, in all the expressions depending on the signal S. Signal suppression is not compatible with timing back-annotation. Expression simplification is always applied after signal suppression.