12. Analog Blocks Handling

12. 1. Objective

HITAS is designed to compute propagation delays in digital designs. The advantage of this restrictive target is to enable very fast computing times. The drawback is that non-digital block characterization is not directly handled by HITAS and should be supplied to 3rd-party analog simulators. However, HITAS provides various ways to link with external characterizations.

This example presents two of the simplest ways with which HITAS can deal with analog blocks. It takes place in the blackbox/ directory.

12. 2. Database Generation

The complete configuration required for the timing database generation takes place the db.tcl script. The temperature and power supplies are specified directly in the circuit.spi file.

12. 3. Ignore Function

The simplest and often sufficient technique for handling analog parts of a design is to tell HITAS to explicitly ignore them so that they will be included in the timing database.

HITAS can ignore specified components with inf_DefineIgnore command. This directive can be used to ignore transistors, instances, resistances, capacitances and diodes by specifying them by name

It is equivalent to commenting out elements in the spice netlist

See HiTas Reference Guide for further details.

inf_SetFigureName circuit
tells the tool to apply the SDC constraints to the design.
inf_DefineIgnore resistances R1
tells the tool to ignore the resistance named R1 in the design.
inf_DefineIgnore instances INV1
tells the tool to ignore the instance inverter named INV1 in the design.

The first ignore directive is to remove what HITAS considers to be a short circuit between the power supplies. A resistance such as this causes problems for the identification of power supply nets and so must be handled like this.

The output logging function has been activated in the db.tcl script for file parsing statistics (see documentation of avtLogFile and avtLogEnable in the reference guide for more details). Look at the generated log file to see the effect of the directive.

The second directive effectively leaves a hole in the netlist, however, this poses no problem for the timing database generation for the rest of the circuit. Try running the path report script (report.tcl) both with and without this directive to see the effect. Leave this directive commented out for the next section.

12. 4. Integration in a Hierarchical Netlist

The second way of handling analog parts is the incorporation of timings from a .lib file to model the timing of a block (anolog or otherwise) instantiated within a hierarchical netlist. In order to use this method it is first of all necessary to create "analog holes" in the netlist where these blocks are instantiated. This is done with the avt_SetBlackBoxes function, taking as argument the list of the sub-circuits to blackbox.

The default behavior of HITAS is not to try to fill the "holes". To tell the tool to fill the holes with timing characterizations, the tasBlackboxRequiresTimings variable is set to yes in the db.tcl script.

The timing information for these "holes" must be provided from an external timing database, this is typically done by loading an appropriate .lib file.

In this example, we will be using an external .lib to represent the timings for the flip-flop. Although this is not really an analog circuit, the procedure would be the same for an analog block and a flip-flop is a simple example containing setup, hold and access arcs.

To try this, you should recreate the timing database with the following lines in the appropriate script:

avt_SetBlackBoxes {msdp2_y}
avt_config tasBlackboxRequiresTimings yes
...
avt_LoadFile ./msdp2_y.lib lib

The timing arcs for the instances msdp2_y are directly integrated in the new database. The database for circuit is flat and does not contain instances of msdp2_y.

Examine the timing database using the path report script and compare with the path reports obtained without "blackboxing" of the flip-flops.