CMSIS-CORE  Version 4.10
CMSIS-CORE support for Cortex-M processor-based devices
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Reference
Here is a list of all modules:
[detail level 12]
oPeripheral AccessDescribes naming conventions, requirements, and optional features for accessing peripherals
oSystem and Clock Configuration
oInterrupts and Exceptions (NVIC)Describes programming of interrupts and exception functions
oCore Register Access
oIntrinsic Functions for CPU Instructions
oIntrinsic Functions for SIMD Instructions [only Cortex-M4 and Cortex-M7]Access to dedicated SIMD instructions
oSystick Timer (SYSTICK)Initialize and start the SysTick timer
oDebug Access
oFPU Functions (only Cortex-M7)
\Cache Functions (only Cortex-M7)Functions for instruciton and data cache
 oI-Cache FunctionsFunctions for the instruction cache
 \D-Cache FunctionsFunctions for the data cache